An algorithm for dynamically reconfigurable FPGA placement

Guang Ming Wu; Jai-Ming Lin; Yao Wen Chang

doi:10.1109/ICCD.2001.955075

An algorithm for dynamically reconfigurable FPGA placement

Guang Ming Wu, Jai-Ming Lin, Yao Wen Chang

Department of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

6 Citations (Scopus)

Abstract

In this paper, we introduce a new placement problem movitated by the Dynamically Reconfigurable FPGA (DRFPGA) architectures. Unlike traditional placement, the problem for DRFPGAs must consider the precedence constraints among logic components. For the placement, we develop an effective metric that can consider wirelength, register requirement, and power consumption simultaneously. With the considerations of the new metric and the precedence constraints, we then present a three-stage scheme of partitioning, initial placement generation, and placement refinement to solve the new placement problem. Experimental results show that our placement scheme with the new metric achieves respective improvements of 17.2%, 27.0%, and 35.9% in wirelength, the number of registers, and power consumption requirements, compared with the list scheduling method.

Original language	English
Article number	75
Pages (from-to)	501-504
Number of pages	4
Journal	Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
DOIs	https://doi.org/10.1109/ICCD.2001.955075
Publication status	Published - 2001 Jan 1

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/ICCD.2001.955075

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An algorithm for dynamically reconfigurable FPGA placement

Abstract

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