An all-digital phase-locked loop for digital power management integrated chips

Yu Ming Chung, Chia-Ling Wei

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Citations (Scopus)

Abstract

An all-digital phase-locked loop (ADPLL) for digital power management applications is presented. The conventional RC loop filter is replaced by a digital loop filter, and the conventional analog voltage-controlled oscillator (VCO) is replaced by a digitally controlled oscillator (DCO). The design procedure of the presented ADPLL is similar to the design procedure of a conventional type-□, second-order charge-pump PLL. The ADPLL was implemented by the TSMC 0.18-μm CMOS process, and the measured DCO oscillating frequency range is 87-250 MHz.

Original languageEnglish
Title of host publication2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
Pages2413-2416
Number of pages4
DOIs
Publication statusPublished - 2009 Oct 26
Event2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 - Taipei, Taiwan
Duration: 2009 May 242009 May 27

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Other

Other2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
CountryTaiwan
CityTaipei
Period09-05-2409-05-27

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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