An application-independent delay testing methodology for Island-style FPGA

Yen Lin Peng; Jing Jia Liou; Chih Tsun Huang; Cheng Wen Wu

doi:10.1109/DFTVS.2004.1347873

An application-independent delay testing methodology for Island-style FPGA

Yen Lin Peng, Jing Jia Liou, Chih Tsun Huang, Cheng Wen Wu

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Citations (Scopus)

Abstract

A novel fault model for detecting delay defects of FPGAs is proposed in this paper. Our fault model assumes that a target segment can be covered by a shortest path which is realizable in an FPGA. And the path will guarantee to detect delay defects which affect the performance of the segment. Given the proposed fault model, we also developed a framework to search for the target paths and find appropriate tests, which is independent to the size of FPGAs. Several methods are also proposed to minimize the number of test configurations (the test time). The tests can achieve a high coverage of delay defects with reasonable test time.

Original language	English
Title of host publication	Proceedings - 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Editors	R. Aitken, A. Salsano, R. Velazco, X. Sun
Pages	478-486
Number of pages	9
DOIs	https://doi.org/10.1109/DFTVS.2004.1347873
Publication status	Published - 2004 Dec 1
Event	19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Cannes, France Duration: 2004 Oct 10 → 2004 Oct 13

Publication series

Name	IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
ISSN (Print)	1550-5774

Conference

Conference	19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Country/Territory	France
City	Cannes
Period	04-10-10 → 04-10-13

All Science Journal Classification (ASJC) codes

General Engineering

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10.1109/DFTVS.2004.1347873

Cite this

Peng, Y. L., Liou, J. J., Huang, C. T., & Wu, C. W. (2004). An application-independent delay testing methodology for Island-style FPGA. In R. Aitken, A. Salsano, R. Velazco, & X. Sun (Eds.), Proceedings - 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (pp. 478-486). (IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems). https://doi.org/10.1109/DFTVS.2004.1347873

Peng, Yen Lin ; Liou, Jing Jia ; Huang, Chih Tsun et al. / An application-independent delay testing methodology for Island-style FPGA. Proceedings - 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. editor / R. Aitken ; A. Salsano ; R. Velazco ; X. Sun. 2004. pp. 478-486 (IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems).

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title = "An application-independent delay testing methodology for Island-style FPGA",

abstract = "A novel fault model for detecting delay defects of FPGAs is proposed in this paper. Our fault model assumes that a target segment can be covered by a shortest path which is realizable in an FPGA. And the path will guarantee to detect delay defects which affect the performance of the segment. Given the proposed fault model, we also developed a framework to search for the target paths and find appropriate tests, which is independent to the size of FPGAs. Several methods are also proposed to minimize the number of test configurations (the test time). The tests can achieve a high coverage of delay defects with reasonable test time.",

author = "Peng, {Yen Lin} and Liou, {Jing Jia} and Huang, {Chih Tsun} and Wu, {Cheng Wen}",

year = "2004",

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booktitle = "Proceedings - 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems",

note = "19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems ; Conference date: 10-10-2004 Through 13-10-2004",

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Peng, YL, Liou, JJ, Huang, CT & Wu, CW 2004, An application-independent delay testing methodology for Island-style FPGA. in R Aitken, A Salsano, R Velazco & X Sun (eds), Proceedings - 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 478-486, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Cannes, France, 04-10-10. https://doi.org/10.1109/DFTVS.2004.1347873

An application-independent delay testing methodology for Island-style FPGA. / Peng, Yen Lin; Liou, Jing Jia; Huang, Chih Tsun et al.
Proceedings - 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. ed. / R. Aitken; A. Salsano; R. Velazco; X. Sun. 2004. p. 478-486 (IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AB - A novel fault model for detecting delay defects of FPGAs is proposed in this paper. Our fault model assumes that a target segment can be covered by a shortest path which is realizable in an FPGA. And the path will guarantee to detect delay defects which affect the performance of the segment. Given the proposed fault model, we also developed a framework to search for the target paths and find appropriate tests, which is independent to the size of FPGAs. Several methods are also proposed to minimize the number of test configurations (the test time). The tests can achieve a high coverage of delay defects with reasonable test time.

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Peng YL, Liou JJ, Huang CT, Wu CW. An application-independent delay testing methodology for Island-style FPGA. In Aitken R, Salsano A, Velazco R, Sun X, editors, Proceedings - 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. 2004. p. 478-486. (IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems). doi: 10.1109/DFTVS.2004.1347873

An application-independent delay testing methodology for Island-style FPGA

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