An area- and power-efficient half-rate clock and data recovery circuit

Yen Long Lee, Soon-Jyh Chang, Rong Sing Chu, Yen Chi Chen, Jih Ren Goh, Chung-Ming Huang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

This paper presents a 3.2 Gb/s low-power clock and data recovery (CDR). The improved architecture using two half-rate gated voltage-controlled oscillators (GVCOs) shared between frequency presetting and data recovery modes is presented to remove the LC-tank voltage-controlled oscillator in a cascaded CDR. Moreover, using the proposed active inductive loading technique instead of the on-chip inductor reduces the power consumption and area in high-speed operation. This CDR circuit has been designed in TSMC 0.18 μm CMOS technology. It consumes 22.5 mW from a 1.8-V supply and occupies an active area of 0.26 mm 2. The peak-to-peak and rms jitter of the recovered clock are 95.6 ps and 12.1 ps for a 3.2 Gb/s 27-1 PRBS, respectively.

Original languageEnglish
Title of host publication2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages2129-2132
Number of pages4
ISBN (Print)9781479934324
DOIs
Publication statusPublished - 2014 Jan 1
Event2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 - Melbourne, VIC, Australia
Duration: 2014 Jun 12014 Jun 5

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Other

Other2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
CountryAustralia
CityMelbourne, VIC
Period14-06-0114-06-05

Fingerprint

Clock and data recovery circuits (CDR circuits)
Clocks
Variable frequency oscillators
Recovery
Jitter
Electric power utilization

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Lee, Y. L., Chang, S-J., Chu, R. S., Chen, Y. C., Goh, J. R., & Huang, C-M. (2014). An area- and power-efficient half-rate clock and data recovery circuit. In 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 (pp. 2129-2132). [6865588] (Proceedings - IEEE International Symposium on Circuits and Systems). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2014.6865588
Lee, Yen Long ; Chang, Soon-Jyh ; Chu, Rong Sing ; Chen, Yen Chi ; Goh, Jih Ren ; Huang, Chung-Ming. / An area- and power-efficient half-rate clock and data recovery circuit. 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014. Institute of Electrical and Electronics Engineers Inc., 2014. pp. 2129-2132 (Proceedings - IEEE International Symposium on Circuits and Systems).
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Lee, YL, Chang, S-J, Chu, RS, Chen, YC, Goh, JR & Huang, C-M 2014, An area- and power-efficient half-rate clock and data recovery circuit. in 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014., 6865588, Proceedings - IEEE International Symposium on Circuits and Systems, Institute of Electrical and Electronics Engineers Inc., pp. 2129-2132, 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014, Melbourne, VIC, Australia, 14-06-01. https://doi.org/10.1109/ISCAS.2014.6865588

An area- and power-efficient half-rate clock and data recovery circuit. / Lee, Yen Long; Chang, Soon-Jyh; Chu, Rong Sing; Chen, Yen Chi; Goh, Jih Ren; Huang, Chung-Ming.

2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014. Institute of Electrical and Electronics Engineers Inc., 2014. p. 2129-2132 6865588 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Lee YL, Chang S-J, Chu RS, Chen YC, Goh JR, Huang C-M. An area- and power-efficient half-rate clock and data recovery circuit. In 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014. Institute of Electrical and Electronics Engineers Inc. 2014. p. 2129-2132. 6865588. (Proceedings - IEEE International Symposium on Circuits and Systems). https://doi.org/10.1109/ISCAS.2014.6865588