An area-efficient color demosaicking scheme for vlsi architecture

In this paper, we propose an efficient demosaicking design, which achieves good image quality with very low computational complexity and less line-buffer memory. Our demosaicking scheme exploits both edge information and inter-channel correlations to improve the quality of the interpolated image. Furthermore, we develop a tight and low-cost VLSI architecture for the scheme by using the resource sharing and pipeline scheduling approaches. Compared with previous demosaicking designs, our circuit requires the least hardware cost and performs well in terms of PSNR and visual quality. ICIC International