An area-efficient color demosaicking scheme for vlsi architecture

Yeu Horng Shiau, Pei-Yin Chen, Chia Wen Chang

Research output: Contribution to journalArticle

9 Citations (Scopus)

Abstract

In this paper, we propose an efficient demosaicking design, which achieves good image quality with very low computational complexity and less line-buffer memory. Our demosaicking scheme exploits both edge information and inter-channel correlations to improve the quality of the interpolated image. Furthermore, we develop a tight and low-cost VLSI architecture for the scheme by using the resource sharing and pipeline scheduling approaches. Compared with previous demosaicking designs, our circuit requires the least hardware cost and performs well in terms of PSNR and visual quality. ICIC International

Original languageEnglish
Pages (from-to)1739-1752
Number of pages14
JournalInternational Journal of Innovative Computing, Information and Control
Volume7
Issue number4
Publication statusPublished - 2011 Apr

Fingerprint

VLSI Architecture
Color
Resource Sharing
Circuit Design
Image Quality
Low Complexity
Image quality
Buffer
Costs
Computational complexity
Computational Complexity
Pipelines
Scheduling
Hardware
Data storage equipment
Networks (circuits)
Line
Design
Vision

All Science Journal Classification (ASJC) codes

  • Computational Theory and Mathematics
  • Information Systems
  • Software
  • Theoretical Computer Science

Cite this

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An area-efficient color demosaicking scheme for vlsi architecture. / Shiau, Yeu Horng; Chen, Pei-Yin; Chang, Chia Wen.

In: International Journal of Innovative Computing, Information and Control, Vol. 7, No. 4, 04.2011, p. 1739-1752.

Research output: Contribution to journalArticle

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