An area efficient gate-all-around ring MOSFET

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper proposes an area efficient gate-all-around ring (GAAR) MOSFET structure for vertical integration, which in essence is an arc-shaped double-gate FinFET and gains benefits of the superior gate control in GAA MOSFETs and feasible manufacturability. Such new structure offers another advantage of tunable performance by changing the size of the ring, giving a simple circuit design flexibility for various performance need for SoC application, especially for vertical transistors with the same gate length. It is shown that a 40% reduction in area is achieved using the vertical GAAR, as compared with conventional multi-fin MOSFETs.

Original languageEnglish
Title of host publication2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages118-119
Number of pages2
ISBN (Electronic)9781509007264
DOIs
Publication statusPublished - 2016 Sep 27
Event21st IEEE Silicon Nanoelectronics Workshop, SNW 2016 - Honolulu, United States
Duration: 2016 Jun 122016 Jun 13

Publication series

Name2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016

Other

Other21st IEEE Silicon Nanoelectronics Workshop, SNW 2016
CountryUnited States
CityHonolulu
Period16-06-1216-06-13

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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