TY - GEN
T1 - An area efficient gate-all-around ring MOSFET
AU - Huang, Ya Chi
AU - Chiang, Meng Hsueh
AU - Wang, Shui Jinn
PY - 2016/9/27
Y1 - 2016/9/27
N2 - This paper proposes an area efficient gate-all-around ring (GAAR) MOSFET structure for vertical integration, which in essence is an arc-shaped double-gate FinFET and gains benefits of the superior gate control in GAA MOSFETs and feasible manufacturability. Such new structure offers another advantage of tunable performance by changing the size of the ring, giving a simple circuit design flexibility for various performance need for SoC application, especially for vertical transistors with the same gate length. It is shown that a 40% reduction in area is achieved using the vertical GAAR, as compared with conventional multi-fin MOSFETs.
AB - This paper proposes an area efficient gate-all-around ring (GAAR) MOSFET structure for vertical integration, which in essence is an arc-shaped double-gate FinFET and gains benefits of the superior gate control in GAA MOSFETs and feasible manufacturability. Such new structure offers another advantage of tunable performance by changing the size of the ring, giving a simple circuit design flexibility for various performance need for SoC application, especially for vertical transistors with the same gate length. It is shown that a 40% reduction in area is achieved using the vertical GAAR, as compared with conventional multi-fin MOSFETs.
UR - http://www.scopus.com/inward/record.url?scp=84994706811&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84994706811&partnerID=8YFLogxK
U2 - 10.1109/SNW.2016.7578011
DO - 10.1109/SNW.2016.7578011
M3 - Conference contribution
AN - SCOPUS:84994706811
T3 - 2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016
SP - 118
EP - 119
BT - 2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 21st IEEE Silicon Nanoelectronics Workshop, SNW 2016
Y2 - 12 June 2016 through 13 June 2016
ER -