TY - GEN
T1 - An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires
AU - Huang, Ya Chi
AU - Chiang, Meng Hsueh
AU - Wang, Shui Jinn
AU - Gupta, Sumeet Kumar
N1 - Publisher Copyright:
© 2018 IEEE.
PY - 2018/6/27
Y1 - 2018/6/27
N2 - An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires is proposed. Among emerging CMOS devices, nanowire (NW) / gate-all-around (GAA) silicon MOSFETs have shown advantages for scaling features as the semiconductor technology continues to progress. While preserving the intrinsic GAA advantages, this paper provides a design methodology for the optimal and feasible manufacturability with different doping concentrations to achieve high density design and assesses the performance via three-dimensional TCAD simulation. However, due to limited atoms in the extremely scaled channel, a heavy doping with in-situ doping process is needed. In addition, using vertical stacked gate-all-around MOSFETs to achieve high density in the same layout area with the proposed multi-threshold doping scheme is beneficial for system on chip (SoC) application. Circuit performance projection of the 6-T SRAM is provided based on balanced read and write performances.
AB - An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires is proposed. Among emerging CMOS devices, nanowire (NW) / gate-all-around (GAA) silicon MOSFETs have shown advantages for scaling features as the semiconductor technology continues to progress. While preserving the intrinsic GAA advantages, this paper provides a design methodology for the optimal and feasible manufacturability with different doping concentrations to achieve high density design and assesses the performance via three-dimensional TCAD simulation. However, due to limited atoms in the extremely scaled channel, a heavy doping with in-situ doping process is needed. In addition, using vertical stacked gate-all-around MOSFETs to achieve high density in the same layout area with the proposed multi-threshold doping scheme is beneficial for system on chip (SoC) application. Circuit performance projection of the 6-T SRAM is provided based on balanced read and write performances.
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U2 - 10.1109/ICICDT.2018.8399770
DO - 10.1109/ICICDT.2018.8399770
M3 - Conference contribution
AN - SCOPUS:85050298395
T3 - ICICDT 2018 - International Conference on IC Design and Technology, Proceedings
SP - 117
EP - 120
BT - ICICDT 2018 - International Conference on IC Design and Technology, Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2018 International Conference on IC Design and Technology, ICICDT 2018
Y2 - 4 June 2018 through 6 June 2018
ER -