An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires

Ya Chi Huang, Meng-Hsueh Chiang, Shui-Jinn Wang, Sumeet Kumar Gupta

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires is proposed. Among emerging CMOS devices, nanowire (NW) / gate-all-around (GAA) silicon MOSFETs have shown advantages for scaling features as the semiconductor technology continues to progress. While preserving the intrinsic GAA advantages, this paper provides a design methodology for the optimal and feasible manufacturability with different doping concentrations to achieve high density design and assesses the performance via three-dimensional TCAD simulation. However, due to limited atoms in the extremely scaled channel, a heavy doping with in-situ doping process is needed. In addition, using vertical stacked gate-all-around MOSFETs to achieve high density in the same layout area with the proposed multi-threshold doping scheme is beneficial for system on chip (SoC) application. Circuit performance projection of the 6-T SRAM is provided based on balanced read and write performances.

Original languageEnglish
Title of host publicationICICDT 2018 - International Conference on IC Design and Technology, Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages117-120
Number of pages4
ISBN (Electronic)9781538625491
DOIs
Publication statusPublished - 2018 Jun 27
Event2018 International Conference on IC Design and Technology, ICICDT 2018 - Otranto, Italy
Duration: 2018 Jun 42018 Jun 6

Publication series

NameICICDT 2018 - International Conference on IC Design and Technology, Proceedings

Other

Other2018 International Conference on IC Design and Technology, ICICDT 2018
CountryItaly
CityOtranto
Period18-06-0418-06-06

Fingerprint

Static random access storage
Nanowires
Doping (additives)
Silicon
Electric potential
Semiconductor materials
Atoms
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

Cite this

Huang, Y. C., Chiang, M-H., Wang, S-J., & Gupta, S. K. (2018). An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires. In ICICDT 2018 - International Conference on IC Design and Technology, Proceedings (pp. 117-120). (ICICDT 2018 - International Conference on IC Design and Technology, Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICICDT.2018.8399770
Huang, Ya Chi ; Chiang, Meng-Hsueh ; Wang, Shui-Jinn ; Gupta, Sumeet Kumar. / An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires. ICICDT 2018 - International Conference on IC Design and Technology, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 117-120 (ICICDT 2018 - International Conference on IC Design and Technology, Proceedings).
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Huang, YC, Chiang, M-H, Wang, S-J & Gupta, SK 2018, An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires. in ICICDT 2018 - International Conference on IC Design and Technology, Proceedings. ICICDT 2018 - International Conference on IC Design and Technology, Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 117-120, 2018 International Conference on IC Design and Technology, ICICDT 2018, Otranto, Italy, 18-06-04. https://doi.org/10.1109/ICICDT.2018.8399770

An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires. / Huang, Ya Chi; Chiang, Meng-Hsueh; Wang, Shui-Jinn; Gupta, Sumeet Kumar.

ICICDT 2018 - International Conference on IC Design and Technology, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. p. 117-120 (ICICDT 2018 - International Conference on IC Design and Technology, Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Huang YC, Chiang M-H, Wang S-J, Gupta SK. An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires. In ICICDT 2018 - International Conference on IC Design and Technology, Proceedings. Institute of Electrical and Electronics Engineers Inc. 2018. p. 117-120. (ICICDT 2018 - International Conference on IC Design and Technology, Proceedings). https://doi.org/10.1109/ICICDT.2018.8399770