Abstract
We present a novel area-efficient parallel-in parallel-out systolic division circuit (v = a/b) over GF(2m) based on the extended Stein's algorithm. By keeping the combined area-time (AT) complexity at the lowest level of O(m2), we evenly distribute the complexity of O(m) in area and time, and design a well-balanced division circuit capable of operating at high speed with high area efficiency. Compared to the other systolic architectures, our design exhibits significant advantages in both area and time.
| Original language | English |
|---|---|
| Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
| Volume | 5 |
| Publication status | Published - 2002 Jan 1 |
| Event | 2002 IEEE International Symposium on Circuits and Systems - Phoenix, AZ, United States Duration: 2002 May 26 → 2002 May 29 |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
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An area-efficient systolic division circuit over GF(2m) for secure communication. / Wu, Chien Hsing; Wu, Chien Ming; Shieh, Ming-Der; Hwang, Yin Tsung.
In: Proceedings - IEEE International Symposium on Circuits and Systems, Vol. 5, 01.01.2002.Research output: Contribution to journal › Conference article
TY - JOUR
T1 - An area-efficient systolic division circuit over GF(2m) for secure communication
AU - Wu, Chien Hsing
AU - Wu, Chien Ming
AU - Shieh, Ming-Der
AU - Hwang, Yin Tsung
PY - 2002/1/1
Y1 - 2002/1/1
N2 - We present a novel area-efficient parallel-in parallel-out systolic division circuit (v = a/b) over GF(2m) based on the extended Stein's algorithm. By keeping the combined area-time (AT) complexity at the lowest level of O(m2), we evenly distribute the complexity of O(m) in area and time, and design a well-balanced division circuit capable of operating at high speed with high area efficiency. Compared to the other systolic architectures, our design exhibits significant advantages in both area and time.
AB - We present a novel area-efficient parallel-in parallel-out systolic division circuit (v = a/b) over GF(2m) based on the extended Stein's algorithm. By keeping the combined area-time (AT) complexity at the lowest level of O(m2), we evenly distribute the complexity of O(m) in area and time, and design a well-balanced division circuit capable of operating at high speed with high area efficiency. Compared to the other systolic architectures, our design exhibits significant advantages in both area and time.
UR - http://www.scopus.com/inward/record.url?scp=0036287913&partnerID=8YFLogxK
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M3 - Conference article
AN - SCOPUS:0036287913
VL - 5
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
SN - 0271-4310
ER -