An area-efficient systolic division circuit over GF(2m) for secure communication

Chien Hsing Wu, Chien Ming Wu, Ming-Der Shieh, Yin Tsung Hwang

Research output: Contribution to journalConference article

15 Citations (Scopus)

Abstract

We present a novel area-efficient parallel-in parallel-out systolic division circuit (v = a/b) over GF(2m) based on the extended Stein's algorithm. By keeping the combined area-time (AT) complexity at the lowest level of O(m2), we evenly distribute the complexity of O(m) in area and time, and design a well-balanced division circuit capable of operating at high speed with high area efficiency. Compared to the other systolic architectures, our design exhibits significant advantages in both area and time.

Original languageEnglish
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume5
Publication statusPublished - 2002 Jan 1
Event2002 IEEE International Symposium on Circuits and Systems - Phoenix, AZ, United States
Duration: 2002 May 262002 May 29

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Networks (circuits)
Secure communication

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

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An area-efficient systolic division circuit over GF(2m) for secure communication. / Wu, Chien Hsing; Wu, Chien Ming; Shieh, Ming-Der; Hwang, Yin Tsung.

In: Proceedings - IEEE International Symposium on Circuits and Systems, Vol. 5, 01.01.2002.

Research output: Contribution to journalConference article

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AU - Wu, Chien Ming

AU - Shieh, Ming-Der

AU - Hwang, Yin Tsung

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N2 - We present a novel area-efficient parallel-in parallel-out systolic division circuit (v = a/b) over GF(2m) based on the extended Stein's algorithm. By keeping the combined area-time (AT) complexity at the lowest level of O(m2), we evenly distribute the complexity of O(m) in area and time, and design a well-balanced division circuit capable of operating at high speed with high area efficiency. Compared to the other systolic architectures, our design exhibits significant advantages in both area and time.

AB - We present a novel area-efficient parallel-in parallel-out systolic division circuit (v = a/b) over GF(2m) based on the extended Stein's algorithm. By keeping the combined area-time (AT) complexity at the lowest level of O(m2), we evenly distribute the complexity of O(m) in area and time, and design a well-balanced division circuit capable of operating at high speed with high area efficiency. Compared to the other systolic architectures, our design exhibits significant advantages in both area and time.

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