We present a novel area-efficient parallel-in parallel-out systolic division circuit (v = a/b) over GF(2m) based on the extended Stein's algorithm. By keeping the combined area-time (AT) complexity at the lowest level of O(m2), we evenly distribute the complexity of O(m) in area and time, and design a well-balanced division circuit capable of operating at high speed with high area efficiency. Compared to the other systolic architectures, our design exhibits significant advantages in both area and time.
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|Publication status||Published - 2002 Jan 1|
|Event||2002 IEEE International Symposium on Circuits and Systems - Phoenix, AZ, United States|
Duration: 2002 May 26 → 2002 May 29
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering