An asynchronous binary-search ADC architecture with a reduced comparator count

Ying Zu Lin, Soon-Jyh Chang, Yen Ting Liu, Chun Cheng Liu, Guan Ying Huang

Research output: Contribution to journalArticlepeer-review

40 Citations (Scopus)

Abstract

This paper reports an asynchronous binary-search analog-to-digital converter (ADC) with reference range prediction. An original N-bit binary-search ADC requires 2N - 1 comparators while the proposed one only needs 2N - 1 ones. Compared to the (high speed, high power) flash ADC and (low speed, low power) successive approximation register ADC, the proposed architecture achieves the balance between power consumption and operation speed. The proof-of-concept 5-bit prototype only consists of a passive track-and-hold circuit, a reference ladder, 9 comparators, 56 switches and 26 static logic gates. This compact ADC occupies an active area of 120 × 50 μm 2 and consumes 1.97 mW from a 1-V supply. At 800 MS/s, the effective number of bits is 4.40 bit and the effective resolution bandwidth is 700 MHz. The resultant figure of merit is 116 fJ/conversion-step.

Original languageEnglish
Article number5378479
Pages (from-to)1829-1837
Number of pages9
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume57
Issue number8
DOIs
Publication statusPublished - 2010 Aug 20

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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