TY - JOUR
T1 - An easy-to-use approach for practical bus-based system design
AU - Chen, Chung Ho
AU - Lin, Feng Fu
N1 - Funding Information:
We thank Prof. Arun Somani for reading and commenting on an early draft of this paper. Also, thanks to the anonymous referees who provided helpful inputs to improve the work. This work was supported in part by the funding of NSC85-2213-E-224-021, Taiwan, Republic of China.
PY - 1999/8
Y1 - 1999/8
N2 - We present an easy-to-use model that addresses the practical issues in designing bus-based shared-memory multiprocessor systems. The model relates the shared-bus width, bus cycle time, cache memory, the features of a program execution, and the number of processors on a shared bus to a metric called request utilization. The request utilization is treated as the scaling factor for the effective average waiting processors in computing the queuing delay cycles. Simulation study shows that the model performs very well in estimating the shared bus response time. Using the model, a system designer can quickly decide the number of the processors that a shared bus is able to support effectively, the size of the cache memory a system should use, and the bus cycle time that the main memory system should provide. With the model, we show that the design favors caching the requests for a contention-based medium instead of speeding up the transfers although the same performance can be respectively achieved by the two techniques in a contention-free situation.
AB - We present an easy-to-use model that addresses the practical issues in designing bus-based shared-memory multiprocessor systems. The model relates the shared-bus width, bus cycle time, cache memory, the features of a program execution, and the number of processors on a shared bus to a metric called request utilization. The request utilization is treated as the scaling factor for the effective average waiting processors in computing the queuing delay cycles. Simulation study shows that the model performs very well in estimating the shared bus response time. Using the model, a system designer can quickly decide the number of the processors that a shared bus is able to support effectively, the size of the cache memory a system should use, and the bus cycle time that the main memory system should provide. With the model, we show that the design favors caching the requests for a contention-based medium instead of speeding up the transfers although the same performance can be respectively achieved by the two techniques in a contention-free situation.
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U2 - 10.1109/12.795121
DO - 10.1109/12.795121
M3 - Article
AN - SCOPUS:3042668844
VL - 48
SP - 780
EP - 793
JO - IEEE Transactions on Computers
JF - IEEE Transactions on Computers
SN - 0018-9340
IS - 8
ER -