An effective SDRAM power mode management scheme for performance and energy sensitive embedded systems

Ning Yaun Ker, Chung-Ho Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

We present an effective power mode management scheme used in SDRAM memory controllers. The scheme employs a bus utilization monitoring mechanism to initiate proper operations of SDRAM chips. Our approach reduces energy consumption by actively switching memories to low-power mode at low bus utilization. At higher bus utilization, the scheme switches memories to open page mode to reduce precharge energy as well as program execution time. This bus utilization predictor reduces memory energy consumption without the expense of increasing program execution time. It achieved the performance level of open page policy by consuming 20% less of memory energy.

Original languageEnglish
Title of host publicationProceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages515-518
Number of pages4
ISBN (Electronic)0780376595
DOIs
Publication statusPublished - 2003 Jan 1
EventAsia and South Pacific Design Automation Conference, ASP-DAC 2003 - Kitakyushu, Japan
Duration: 2003 Jan 212003 Jan 24

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume2003-January

Other

OtherAsia and South Pacific Design Automation Conference, ASP-DAC 2003
CountryJapan
CityKitakyushu
Period03-01-2103-01-24

Fingerprint

Embedded systems
Data storage equipment
Energy utilization
Switches
Controllers
Monitoring

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Cite this

Ker, N. Y., & Chen, C-H. (2003). An effective SDRAM power mode management scheme for performance and energy sensitive embedded systems. In Proceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference (pp. 515-518). [1195071] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 2003-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2003.1195071
Ker, Ning Yaun ; Chen, Chung-Ho. / An effective SDRAM power mode management scheme for performance and energy sensitive embedded systems. Proceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference. Institute of Electrical and Electronics Engineers Inc., 2003. pp. 515-518 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).
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Ker, NY & Chen, C-H 2003, An effective SDRAM power mode management scheme for performance and energy sensitive embedded systems. in Proceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference., 1195071, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, vol. 2003-January, Institute of Electrical and Electronics Engineers Inc., pp. 515-518, Asia and South Pacific Design Automation Conference, ASP-DAC 2003, Kitakyushu, Japan, 03-01-21. https://doi.org/10.1109/ASPDAC.2003.1195071

An effective SDRAM power mode management scheme for performance and energy sensitive embedded systems. / Ker, Ning Yaun; Chen, Chung-Ho.

Proceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference. Institute of Electrical and Electronics Engineers Inc., 2003. p. 515-518 1195071 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 2003-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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N2 - We present an effective power mode management scheme used in SDRAM memory controllers. The scheme employs a bus utilization monitoring mechanism to initiate proper operations of SDRAM chips. Our approach reduces energy consumption by actively switching memories to low-power mode at low bus utilization. At higher bus utilization, the scheme switches memories to open page mode to reduce precharge energy as well as program execution time. This bus utilization predictor reduces memory energy consumption without the expense of increasing program execution time. It achieved the performance level of open page policy by consuming 20% less of memory energy.

AB - We present an effective power mode management scheme used in SDRAM memory controllers. The scheme employs a bus utilization monitoring mechanism to initiate proper operations of SDRAM chips. Our approach reduces energy consumption by actively switching memories to low-power mode at low bus utilization. At higher bus utilization, the scheme switches memories to open page mode to reduce precharge energy as well as program execution time. This bus utilization predictor reduces memory energy consumption without the expense of increasing program execution time. It achieved the performance level of open page policy by consuming 20% less of memory energy.

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Ker NY, Chen C-H. An effective SDRAM power mode management scheme for performance and energy sensitive embedded systems. In Proceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference. Institute of Electrical and Electronics Engineers Inc. 2003. p. 515-518. 1195071. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2003.1195071