An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST

Liang Che Li, Wen Hsuan Hsu, Kuen Jong Lee, Chun Lung Hsu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

TSV-based 3D-IC design can reduce the connection length of stacked ICs and enhance I/O bandwidth of heterogeneous integrated circuits. However the testing of 3D ICs is more complicated than that of 2D ICs. This paper presents an efficient on-chip 3D-IC test framework that can embed the test procedure of TSVs into the memory BIST process. By using the same test patterns generated from the memory BIST mechanism, the faults in both memories and TSVs can be detected simultaneously without extra time to test TSVs. The area overhead for on-chip testing can also be reduced significantly. Experimental results show that the proposed test framework can gain a good performance in test time reduction with very low area overhead penalty for a memory-logic stacked IC.

Original languageEnglish
Title of host publication20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages520-525
Number of pages6
ISBN (Electronic)9781479977925
DOIs
Publication statusPublished - 2015 Mar 11
Event2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 - Chiba, Japan
Duration: 2015 Jan 192015 Jan 22

Publication series

Name20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015

Other

Other2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
CountryJapan
CityChiba
Period15-01-1915-01-22

Fingerprint

Built-in self test
Chip
Data storage equipment
Testing
Integrated circuits
Integrated Circuits
Bandwidth
Penalty
Framework
Fault
Logic
Experimental Results

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Electrical and Electronic Engineering
  • Control and Systems Engineering
  • Modelling and Simulation

Cite this

Li, L. C., Hsu, W. H., Lee, K. J., & Hsu, C. L. (2015). An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST. In 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 (pp. 520-525). [7059059] (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2015.7059059
Li, Liang Che ; Hsu, Wen Hsuan ; Lee, Kuen Jong ; Hsu, Chun Lung. / An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST. 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 520-525 (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015).
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Li, LC, Hsu, WH, Lee, KJ & Hsu, CL 2015, An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST. in 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015., 7059059, 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015, Institute of Electrical and Electronics Engineers Inc., pp. 520-525, 2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015, Chiba, Japan, 15-01-19. https://doi.org/10.1109/ASPDAC.2015.7059059

An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST. / Li, Liang Che; Hsu, Wen Hsuan; Lee, Kuen Jong; Hsu, Chun Lung.

20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 520-525 7059059 (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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N2 - TSV-based 3D-IC design can reduce the connection length of stacked ICs and enhance I/O bandwidth of heterogeneous integrated circuits. However the testing of 3D ICs is more complicated than that of 2D ICs. This paper presents an efficient on-chip 3D-IC test framework that can embed the test procedure of TSVs into the memory BIST process. By using the same test patterns generated from the memory BIST mechanism, the faults in both memories and TSVs can be detected simultaneously without extra time to test TSVs. The area overhead for on-chip testing can also be reduced significantly. Experimental results show that the proposed test framework can gain a good performance in test time reduction with very low area overhead penalty for a memory-logic stacked IC.

AB - TSV-based 3D-IC design can reduce the connection length of stacked ICs and enhance I/O bandwidth of heterogeneous integrated circuits. However the testing of 3D ICs is more complicated than that of 2D ICs. This paper presents an efficient on-chip 3D-IC test framework that can embed the test procedure of TSVs into the memory BIST process. By using the same test patterns generated from the memory BIST mechanism, the faults in both memories and TSVs can be detected simultaneously without extra time to test TSVs. The area overhead for on-chip testing can also be reduced significantly. Experimental results show that the proposed test framework can gain a good performance in test time reduction with very low area overhead penalty for a memory-logic stacked IC.

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Li LC, Hsu WH, Lee KJ, Hsu CL. An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST. In 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 520-525. 7059059. (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015). https://doi.org/10.1109/ASPDAC.2015.7059059