An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST

Liang Che Li; Wen Hsuan Hsu; Kuen Jong Lee; Chun Lung Hsu

doi:10.1109/ASPDAC.2015.7059059

An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST

Liang Che Li, Wen Hsuan Hsu, Kuen Jong Lee, Chun Lung Hsu

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

14 Citations (Scopus)

Abstract

TSV-based 3D-IC design can reduce the connection length of stacked ICs and enhance I/O bandwidth of heterogeneous integrated circuits. However the testing of 3D ICs is more complicated than that of 2D ICs. This paper presents an efficient on-chip 3D-IC test framework that can embed the test procedure of TSVs into the memory BIST process. By using the same test patterns generated from the memory BIST mechanism, the faults in both memories and TSVs can be detected simultaneously without extra time to test TSVs. The area overhead for on-chip testing can also be reduced significantly. Experimental results show that the proposed test framework can gain a good performance in test time reduction with very low area overhead penalty for a memory-logic stacked IC.

Original language	English
Title of host publication	20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	520-525
Number of pages	6
ISBN (Electronic)	9781479977925
DOIs	https://doi.org/10.1109/ASPDAC.2015.7059059
Publication status	Published - 2015 Mar 11
Event	2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 - Chiba, Japan Duration: 2015 Jan 19 → 2015 Jan 22

Publication series

Name	20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015

Other

Other	2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
Country/Territory	Japan
City	Chiba
Period	15-01-19 → 15-01-22

All Science Journal Classification (ASJC) codes

Computer Science Applications
Electrical and Electronic Engineering
Control and Systems Engineering
Modelling and Simulation

Access to Document

10.1109/ASPDAC.2015.7059059

Cite this

Li, L. C., Hsu, W. H., Lee, K. J., & Hsu, C. L. (2015). An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST. In 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 (pp. 520-525). Article 7059059 (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2015.7059059

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abstract = "TSV-based 3D-IC design can reduce the connection length of stacked ICs and enhance I/O bandwidth of heterogeneous integrated circuits. However the testing of 3D ICs is more complicated than that of 2D ICs. This paper presents an efficient on-chip 3D-IC test framework that can embed the test procedure of TSVs into the memory BIST process. By using the same test patterns generated from the memory BIST mechanism, the faults in both memories and TSVs can be detected simultaneously without extra time to test TSVs. The area overhead for on-chip testing can also be reduced significantly. Experimental results show that the proposed test framework can gain a good performance in test time reduction with very low area overhead penalty for a memory-logic stacked IC.",

author = "Li, {Liang Che} and Hsu, {Wen Hsuan} and Lee, {Kuen Jong} and Hsu, {Chun Lung}",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 ; Conference date: 19-01-2015 Through 22-01-2015",

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series = "20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015",

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Li, LC, Hsu, WH, Lee, KJ & Hsu, CL 2015, An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST. in 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015., 7059059, 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015, Institute of Electrical and Electronics Engineers Inc., pp. 520-525, 2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015, Chiba, Japan, 15-01-19. https://doi.org/10.1109/ASPDAC.2015.7059059

An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST. / Li, Liang Che; Hsu, Wen Hsuan; Lee, Kuen Jong et al.
20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 520-525 7059059 (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Li, Liang Che

AU - Hsu, Wen Hsuan

AU - Lee, Kuen Jong

AU - Hsu, Chun Lung

PY - 2015/3/11

Y1 - 2015/3/11

N2 - TSV-based 3D-IC design can reduce the connection length of stacked ICs and enhance I/O bandwidth of heterogeneous integrated circuits. However the testing of 3D ICs is more complicated than that of 2D ICs. This paper presents an efficient on-chip 3D-IC test framework that can embed the test procedure of TSVs into the memory BIST process. By using the same test patterns generated from the memory BIST mechanism, the faults in both memories and TSVs can be detected simultaneously without extra time to test TSVs. The area overhead for on-chip testing can also be reduced significantly. Experimental results show that the proposed test framework can gain a good performance in test time reduction with very low area overhead penalty for a memory-logic stacked IC.

AB - TSV-based 3D-IC design can reduce the connection length of stacked ICs and enhance I/O bandwidth of heterogeneous integrated circuits. However the testing of 3D ICs is more complicated than that of 2D ICs. This paper presents an efficient on-chip 3D-IC test framework that can embed the test procedure of TSVs into the memory BIST process. By using the same test patterns generated from the memory BIST mechanism, the faults in both memories and TSVs can be detected simultaneously without extra time to test TSVs. The area overhead for on-chip testing can also be reduced significantly. Experimental results show that the proposed test framework can gain a good performance in test time reduction with very low area overhead penalty for a memory-logic stacked IC.

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Li LC, Hsu WH, Lee KJ, Hsu CL. An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST. In 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 520-525. 7059059. (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015). doi: 10.1109/ASPDAC.2015.7059059

An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST

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