An efficient architecture for deblocking filter in H.264/AVC video coding

Chung Ming Chen, Chung Ho Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Citations (Scopus)

Abstract

In this paper, we propose an efficient architecture for the adaptive deblocking filter in H.264/AVC video coding standard. We use eight forwarding shift register arrays (of which each contains 4×4 8-bit shift registers) with two transposing operations and two filter units to support simultaneous processing of the horizontal and vertical filtering. The proposed architecture is called "Pipeline Buffer Shift Register (PBSR)." As a result, the performance of PBSR is 22.5% faster than the advanced architecture of the previous proposal. Moreover, the number of total memory references is reduced to 37% and 75% respectively compared to the basic and advanced architectures of the previous proposals.

Original languageEnglish
Title of host publicationProceedings of the Eighth IASTED International Conference on Computer Graphics and Imaging, CGIM 2005
EditorsM.H. Hamza
Pages177-181
Number of pages5
Publication statusPublished - 2005 Dec 1
EventEighth IASTED International Conference on Computer Graphics and Imaging, CGIM 2005 - Honolulu, HI, United States
Duration: 2005 Aug 152005 Aug 17

Publication series

NameProceedings of the Eighth IASTED International Conference on Computer Graphics and Imaging, CGIM 2005

Other

OtherEighth IASTED International Conference on Computer Graphics and Imaging, CGIM 2005
CountryUnited States
CityHonolulu, HI
Period05-08-1505-08-17

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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