An efficient architecture for deblocking filter in H.264/AVC video coding

Chung Ming Chen; Chung Ho Chen

An efficient architecture for deblocking filter in H.264/AVC video coding

Chung Ming Chen, Chung Ho Chen

Institute of Computer and Communication Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

15 Citations (Scopus)

Abstract

In this paper, we propose an efficient architecture for the adaptive deblocking filter in H.264/AVC video coding standard. We use eight forwarding shift register arrays (of which each contains 4×4 8-bit shift registers) with two transposing operations and two filter units to support simultaneous processing of the horizontal and vertical filtering. The proposed architecture is called "Pipeline Buffer Shift Register (PBSR)." As a result, the performance of PBSR is 22.5% faster than the advanced architecture of the previous proposal. Moreover, the number of total memory references is reduced to 37% and 75% respectively compared to the basic and advanced architectures of the previous proposals.

Original language	English
Title of host publication	Proceedings of the Eighth IASTED International Conference on Computer Graphics and Imaging, CGIM 2005
Editors	M.H. Hamza
Pages	177-181
Number of pages	5
Publication status	Published - 2005 Dec 1
Event	Eighth IASTED International Conference on Computer Graphics and Imaging, CGIM 2005 - Honolulu, HI, United States Duration: 2005 Aug 15 → 2005 Aug 17

Publication series

Name	Proceedings of the Eighth IASTED International Conference on Computer Graphics and Imaging, CGIM 2005

Other

Other	Eighth IASTED International Conference on Computer Graphics and Imaging, CGIM 2005
Country	United States
City	Honolulu, HI
Period	05-08-15 → 05-08-17

All Science Journal Classification (ASJC) codes

Engineering(all)

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Cite this

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title = "An efficient architecture for deblocking filter in H.264/AVC video coding",

abstract = "In this paper, we propose an efficient architecture for the adaptive deblocking filter in H.264/AVC video coding standard. We use eight forwarding shift register arrays (of which each contains 4×4 8-bit shift registers) with two transposing operations and two filter units to support simultaneous processing of the horizontal and vertical filtering. The proposed architecture is called {"}Pipeline Buffer Shift Register (PBSR).{"} As a result, the performance of PBSR is 22.5% faster than the advanced architecture of the previous proposal. Moreover, the number of total memory references is reduced to 37% and 75% respectively compared to the basic and advanced architectures of the previous proposals.",

author = "Chen, {Chung Ming} and Chen, {Chung Ho}",

year = "2005",

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note = "Eighth IASTED International Conference on Computer Graphics and Imaging, CGIM 2005 ; Conference date: 15-08-2005 Through 17-08-2005",

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Chen, CM & Chen, CH 2005, An efficient architecture for deblocking filter in H.264/AVC video coding. in MH Hamza (ed.), Proceedings of the Eighth IASTED International Conference on Computer Graphics and Imaging, CGIM 2005. Proceedings of the Eighth IASTED International Conference on Computer Graphics and Imaging, CGIM 2005, pp. 177-181, Eighth IASTED International Conference on Computer Graphics and Imaging, CGIM 2005, Honolulu, HI, United States, 05-08-15.

An efficient architecture for deblocking filter in H.264/AVC video coding. / Chen, Chung Ming; Chen, Chung Ho.

Proceedings of the Eighth IASTED International Conference on Computer Graphics and Imaging, CGIM 2005. ed. / M.H. Hamza. 2005. p. 177-181 (Proceedings of the Eighth IASTED International Conference on Computer Graphics and Imaging, CGIM 2005).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AB - In this paper, we propose an efficient architecture for the adaptive deblocking filter in H.264/AVC video coding standard. We use eight forwarding shift register arrays (of which each contains 4×4 8-bit shift registers) with two transposing operations and two filter units to support simultaneous processing of the horizontal and vertical filtering. The proposed architecture is called "Pipeline Buffer Shift Register (PBSR)." As a result, the performance of PBSR is 22.5% faster than the advanced architecture of the previous proposal. Moreover, the number of total memory references is reduced to 37% and 75% respectively compared to the basic and advanced architectures of the previous proposals.

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