TY - GEN
T1 - An efficient architecture for deblocking filter in H.264/AVC video coding
AU - Chen, Chung Ming
AU - Chen, Chung Ho
PY - 2005/12/1
Y1 - 2005/12/1
N2 - In this paper, we propose an efficient architecture for the adaptive deblocking filter in H.264/AVC video coding standard. We use eight forwarding shift register arrays (of which each contains 4×4 8-bit shift registers) with two transposing operations and two filter units to support simultaneous processing of the horizontal and vertical filtering. The proposed architecture is called "Pipeline Buffer Shift Register (PBSR)." As a result, the performance of PBSR is 22.5% faster than the advanced architecture of the previous proposal. Moreover, the number of total memory references is reduced to 37% and 75% respectively compared to the basic and advanced architectures of the previous proposals.
AB - In this paper, we propose an efficient architecture for the adaptive deblocking filter in H.264/AVC video coding standard. We use eight forwarding shift register arrays (of which each contains 4×4 8-bit shift registers) with two transposing operations and two filter units to support simultaneous processing of the horizontal and vertical filtering. The proposed architecture is called "Pipeline Buffer Shift Register (PBSR)." As a result, the performance of PBSR is 22.5% faster than the advanced architecture of the previous proposal. Moreover, the number of total memory references is reduced to 37% and 75% respectively compared to the basic and advanced architectures of the previous proposals.
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M3 - Conference contribution
AN - SCOPUS:33644511377
SN - 0889865140
T3 - Proceedings of the Eighth IASTED International Conference on Computer Graphics and Imaging, CGIM 2005
SP - 177
EP - 181
BT - Proceedings of the Eighth IASTED International Conference on Computer Graphics and Imaging, CGIM 2005
A2 - Hamza, M.H.
T2 - Eighth IASTED International Conference on Computer Graphics and Imaging, CGIM 2005
Y2 - 15 August 2005 through 17 August 2005
ER -