An efficient design-for-testability scheme for 2-D transform in H.264 advanced video coders

Heng Yao Lin, Hui Hsien Tsai, Bin Da Liu, Jar Ferr Yang, Soon Jyh Chang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

In this paper, an easily design-for-testability (DfT) scheme based on C-testability conditions is adopted to implement test syntheses of the 2-D forward, inverse and Hadamard transforms suggested in H.264 advanced video coders (AVC). The proposed testable scheme is applied to bit-level regular arrangement for the transform architecture. It guarantees 100% fault coverage while the resulting number of test pattern is only 8. The proposed integrated transforms have been synthesized with UMC 0.18 μm technology. Under the small performance degradation, simulation results show that the DfT implementation increases about only 12% area overhead compared with the original circuit.

Original languageEnglish
Title of host publicationAPCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
Pages255-258
Number of pages4
DOIs
Publication statusPublished - 2006 Dec 1
EventAPCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems - , Singapore
Duration: 2006 Dec 42006 Dec 6

Publication series

NameIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Other

OtherAPCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
CountrySingapore
Period06-12-0406-12-06

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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