An efficient design of variable length decoder for MPEG-1/2/4

Pei Yin Chen; Yi Ming Lin; Min Yi Cho

doi:10.1109/TMM.2008.2004909

An efficient design of variable length decoder for MPEG-1/2/4

Pei Yin Chen, Yi Ming Lin, Min Yi Cho

Department of Computer Science and Information Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

In this paper, a novel and area-efficient variable length decoder (VLD) for MPEG-1/2/4 is presented. Instead of carrying out every variable length coding table with one dedicated lookup table (LUT) directly, we employ an efficient clustering-merging technique to reduce both the size of a single LUT and the total number of LUTs required for MPEG-1/2/4. Synthesis results show that our VLD occupies 10666 gate counts and operates at 125 MHz by using the standard cell from Artisan TSMC's 0.18 μm process. As demonstrated, the proposed design outperforms other VLDs with less hardware cost. It can decode a symbol of different standards in every cycle and support video resolution of HD1080 at 30 frames/s for MPEG-1/2/4 real-time decoding.

Original language	English
Article number	4668499
Pages (from-to)	1307-1315
Number of pages	9
Journal	IEEE Transactions on Multimedia
Volume	10
Issue number	7
DOIs	https://doi.org/10.1109/TMM.2008.2004909
Publication status	Published - 2008 Nov

All Science Journal Classification (ASJC) codes

Signal Processing
Media Technology
Computer Science Applications
Electrical and Electronic Engineering

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10.1109/TMM.2008.2004909

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title = "An efficient design of variable length decoder for MPEG-1/2/4",

abstract = "In this paper, a novel and area-efficient variable length decoder (VLD) for MPEG-1/2/4 is presented. Instead of carrying out every variable length coding table with one dedicated lookup table (LUT) directly, we employ an efficient clustering-merging technique to reduce both the size of a single LUT and the total number of LUTs required for MPEG-1/2/4. Synthesis results show that our VLD occupies 10666 gate counts and operates at 125 MHz by using the standard cell from Artisan TSMC's 0.18 μm process. As demonstrated, the proposed design outperforms other VLDs with less hardware cost. It can decode a symbol of different standards in every cycle and support video resolution of HD1080 at 30 frames/s for MPEG-1/2/4 real-time decoding.",

author = "Chen, {Pei Yin} and Lin, {Yi Ming} and Cho, {Min Yi}",

note = "Funding Information: Manuscript received January 23, 2008; revised May 22, 2008. Current version published November 17, 2008. This work was supported in part by the National Science Council of Taiwan R.O.C. under Grant NSC-96-2221-E-006-027-MY3. This work made use of Shared Facilities supported by the Program of Top 100 Universities Advancement, Ministry of Education, Taiwan. This paper was recommended by Associate Editor Simon R. Jones.",

year = "2008",

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doi = "10.1109/TMM.2008.2004909",

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N1 - Funding Information: Manuscript received January 23, 2008; revised May 22, 2008. Current version published November 17, 2008. This work was supported in part by the National Science Council of Taiwan R.O.C. under Grant NSC-96-2221-E-006-027-MY3. This work made use of Shared Facilities supported by the Program of Top 100 Universities Advancement, Ministry of Education, Taiwan. This paper was recommended by Associate Editor Simon R. Jones.

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An efficient design of variable length decoder for MPEG-1/2/4

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