An efficient design of variable length decoder for MPEG-1/2/4

Pei Yin Chen, Yi Ming Lin, Min Yi Cho

Research output: Contribution to journalArticlepeer-review


In this paper, a novel and area-efficient variable length decoder (VLD) for MPEG-1/2/4 is presented. Instead of carrying out every variable length coding table with one dedicated lookup table (LUT) directly, we employ an efficient clustering-merging technique to reduce both the size of a single LUT and the total number of LUTs required for MPEG-1/2/4. Synthesis results show that our VLD occupies 10666 gate counts and operates at 125 MHz by using the standard cell from Artisan TSMC's 0.18 μm process. As demonstrated, the proposed design outperforms other VLDs with less hardware cost. It can decode a symbol of different standards in every cycle and support video resolution of HD1080 at 30 frames/s for MPEG-1/2/4 real-time decoding.

Original languageEnglish
Article number4668499
Pages (from-to)1307-1315
Number of pages9
JournalIEEE Transactions on Multimedia
Issue number7
Publication statusPublished - 2008 Nov

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Media Technology
  • Computer Science Applications
  • Electrical and Electronic Engineering


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