An Efficient Diagnosis-Aware ATPG Procedure to Enhance Diagnosis Resolution and Test Compaction

Cheng Hung Wu, Kuen Jong Lee, Sudhakar M. Reddy

Research output: Contribution to journalArticlepeer-review

12 Citations (Scopus)


This paper proposes an efficient diagnosis-aware automatic test pattern generation (ATPG) procedure that can quickly identify equivalent-fault pairs and generate diagnosis patterns (DPs) for nonequivalent-fault pairs, where a (non)equivalent fault pair contains two stuck-at faults that are (non)equivalent. The proposed procedure contains three main methods, which together can efficiently generate highly compacted DPs by using a conventional ATPG tool. First, an all-pairs at-a-time diagnosis pattern generation (AFPAT-DPG) method, which adopts user-defined fault models (UDFMs), is employed to quickly generate DPs for most fault pairs that cannot be distinguished by a given set of, typically fault detection, test patterns (TP). For those fault pairs that cannot be distinguished by AFPAT-DPG, a multipair diagnostic ATPG method (MP-DATPG) is used. MP-DATPG is a complete method in the sense that it can generate diagnosis tests for every distinguishable pair of faults or prove that the pair of faults is indistinguishable. However, due to back-track limits in test generation procedures, diagnosis test generation for some fault pairs may be aborted after the application of the two methods. For such fault pairs, a subcircuit analysis (SCA) method is applied to identify equivalent fault pairs among the aborted fault pairs by trimming the circuit under consideration into one that is much easier to process within the back-track limits of the test generation procedures. Experimental results show that the proposed procedure is the first work that distinguishes 100% of all fault pairs in all ISCAS'89 and IWLS'05 benchmark circuits and over 99.99% for all ITC'99 benchmark circuits using a conventional ATPG tool that generates tests to detect faults.

Original languageEnglish
Article number8742768
Pages (from-to)2105-2118
Number of pages14
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number9
Publication statusPublished - 2019 Sept

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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