An efficient multi-phase test technique to perfectly prevent over-detection of acceptable faults for optimal yield improvement via error-tolerance

Tong Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

In many multimedia applications, some faults induce errors that are user-imperceptible and thus are acceptable. By not testing for these faults, the effective yield can be significantly increased based on the principle of error-tolerance. However, studies have shown that test patterns generated by a conventional ATPG procedure targeting only unacceptable faults also detect many acceptable faults, resulting in a significant degradation in achievable yield improvement. In this paper we present a multi-phase test technique that can perfectly prevent this over-detection problem. Solid theoretical derivations are provided to validate the effectiveness of this technique. Compared with previous work, only a much smaller number of test patterns are required and thus the required test cost can be much lower. Experimental results on benchmark circuits illustrate the high efficiency of this novel technique.

Original languageEnglish
Title of host publication2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
Pages255-258
Number of pages4
DOIs
Publication statusPublished - 2009 Dec 1
Event2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09 - Hsinchu, Taiwan
Duration: 2009 Apr 282009 Apr 30

Publication series

Name2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09

Other

Other2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
CountryTaiwan
CityHsinchu
Period09-04-2809-04-30

Fingerprint

Degradation
Networks (circuits)
Testing
Costs

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

Cite this

Hsieh, T. Y., Lee, K-J., & Breuer, M. A. (2009). An efficient multi-phase test technique to perfectly prevent over-detection of acceptable faults for optimal yield improvement via error-tolerance. In 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09 (pp. 255-258). [5158143] (2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09). https://doi.org/10.1109/VDAT.2009.5158143
Hsieh, Tong Yu ; Lee, Kuen-Jong ; Breuer, Melvin A. / An efficient multi-phase test technique to perfectly prevent over-detection of acceptable faults for optimal yield improvement via error-tolerance. 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09. 2009. pp. 255-258 (2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09).
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Hsieh, TY, Lee, K-J & Breuer, MA 2009, An efficient multi-phase test technique to perfectly prevent over-detection of acceptable faults for optimal yield improvement via error-tolerance. in 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09., 5158143, 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09, pp. 255-258, 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09, Hsinchu, Taiwan, 09-04-28. https://doi.org/10.1109/VDAT.2009.5158143

An efficient multi-phase test technique to perfectly prevent over-detection of acceptable faults for optimal yield improvement via error-tolerance. / Hsieh, Tong Yu; Lee, Kuen-Jong; Breuer, Melvin A.

2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09. 2009. p. 255-258 5158143 (2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Hsieh TY, Lee K-J, Breuer MA. An efficient multi-phase test technique to perfectly prevent over-detection of acceptable faults for optimal yield improvement via error-tolerance. In 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09. 2009. p. 255-258. 5158143. (2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09). https://doi.org/10.1109/VDAT.2009.5158143