An efficient NBTI-aware wake-up strategy for power-gated designs

Kun Wei Chiu, Yu Guang Chen, Ing-Chao Lin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

The wake-up process of a power-gated design may induce an excessive surge current and threaten the signal integrity. A proper wake-up sequence should be carefully designed to avoid surge current violations. On the other hand, PMOS sleep transistors may suffer from the negative-bias temperature instability (NBTI) effect which results in decreased driving current. Conventional wake-up sequence decision approaches do not consider the NBTI effect, which may result in a longer or unacceptable wake-up time after circuit aging. Therefore, in this paper, we propose a novel NBTI-aware wake-up strategy to reduce the average wake-up time within a circuit lifetime. Our strategy first finds a set of proper wake-up sequences for different aging scenarios (i.e. after a certain period of aging), and then dynamically reconfigures the wake-up sequences at runtime. The experimental results show that compared to a traditional fixed wake-up sequence approach, our strategy can reduce average wake-up time by as much as 45.04% with only 3.7% extra area overhead for the reconfiguration structure.

Original languageEnglish
Title of host publicationProceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages901-904
Number of pages4
Volume2018-January
ISBN (Electronic)9783981926316
DOIs
Publication statusPublished - 2018 Apr 19
Event2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018 - Dresden, Germany
Duration: 2018 Mar 192018 Mar 23

Other

Other2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018
CountryGermany
CityDresden
Period18-03-1918-03-23

Fingerprint

Aging of materials
Negative bias temperature instability
Temperature
Networks (circuits)
Transistors
Integrity
Violations
Scenarios
Sleep
Reconfiguration

All Science Journal Classification (ASJC) codes

  • Safety, Risk, Reliability and Quality
  • Hardware and Architecture
  • Software
  • Information Systems and Management

Cite this

Chiu, K. W., Chen, Y. G., & Lin, I-C. (2018). An efficient NBTI-aware wake-up strategy for power-gated designs. In Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018 (Vol. 2018-January, pp. 901-904). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/DATE.2018.8342136
Chiu, Kun Wei ; Chen, Yu Guang ; Lin, Ing-Chao. / An efficient NBTI-aware wake-up strategy for power-gated designs. Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018. Vol. 2018-January Institute of Electrical and Electronics Engineers Inc., 2018. pp. 901-904
@inproceedings{8f8cc28ce25e481ab59d551549a0a8e4,
title = "An efficient NBTI-aware wake-up strategy for power-gated designs",
abstract = "The wake-up process of a power-gated design may induce an excessive surge current and threaten the signal integrity. A proper wake-up sequence should be carefully designed to avoid surge current violations. On the other hand, PMOS sleep transistors may suffer from the negative-bias temperature instability (NBTI) effect which results in decreased driving current. Conventional wake-up sequence decision approaches do not consider the NBTI effect, which may result in a longer or unacceptable wake-up time after circuit aging. Therefore, in this paper, we propose a novel NBTI-aware wake-up strategy to reduce the average wake-up time within a circuit lifetime. Our strategy first finds a set of proper wake-up sequences for different aging scenarios (i.e. after a certain period of aging), and then dynamically reconfigures the wake-up sequences at runtime. The experimental results show that compared to a traditional fixed wake-up sequence approach, our strategy can reduce average wake-up time by as much as 45.04{\%} with only 3.7{\%} extra area overhead for the reconfiguration structure.",
author = "Chiu, {Kun Wei} and Chen, {Yu Guang} and Ing-Chao Lin",
year = "2018",
month = "4",
day = "19",
doi = "10.23919/DATE.2018.8342136",
language = "English",
volume = "2018-January",
pages = "901--904",
booktitle = "Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
address = "United States",

}

Chiu, KW, Chen, YG & Lin, I-C 2018, An efficient NBTI-aware wake-up strategy for power-gated designs. in Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018. vol. 2018-January, Institute of Electrical and Electronics Engineers Inc., pp. 901-904, 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018, Dresden, Germany, 18-03-19. https://doi.org/10.23919/DATE.2018.8342136

An efficient NBTI-aware wake-up strategy for power-gated designs. / Chiu, Kun Wei; Chen, Yu Guang; Lin, Ing-Chao.

Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018. Vol. 2018-January Institute of Electrical and Electronics Engineers Inc., 2018. p. 901-904.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - An efficient NBTI-aware wake-up strategy for power-gated designs

AU - Chiu, Kun Wei

AU - Chen, Yu Guang

AU - Lin, Ing-Chao

PY - 2018/4/19

Y1 - 2018/4/19

N2 - The wake-up process of a power-gated design may induce an excessive surge current and threaten the signal integrity. A proper wake-up sequence should be carefully designed to avoid surge current violations. On the other hand, PMOS sleep transistors may suffer from the negative-bias temperature instability (NBTI) effect which results in decreased driving current. Conventional wake-up sequence decision approaches do not consider the NBTI effect, which may result in a longer or unacceptable wake-up time after circuit aging. Therefore, in this paper, we propose a novel NBTI-aware wake-up strategy to reduce the average wake-up time within a circuit lifetime. Our strategy first finds a set of proper wake-up sequences for different aging scenarios (i.e. after a certain period of aging), and then dynamically reconfigures the wake-up sequences at runtime. The experimental results show that compared to a traditional fixed wake-up sequence approach, our strategy can reduce average wake-up time by as much as 45.04% with only 3.7% extra area overhead for the reconfiguration structure.

AB - The wake-up process of a power-gated design may induce an excessive surge current and threaten the signal integrity. A proper wake-up sequence should be carefully designed to avoid surge current violations. On the other hand, PMOS sleep transistors may suffer from the negative-bias temperature instability (NBTI) effect which results in decreased driving current. Conventional wake-up sequence decision approaches do not consider the NBTI effect, which may result in a longer or unacceptable wake-up time after circuit aging. Therefore, in this paper, we propose a novel NBTI-aware wake-up strategy to reduce the average wake-up time within a circuit lifetime. Our strategy first finds a set of proper wake-up sequences for different aging scenarios (i.e. after a certain period of aging), and then dynamically reconfigures the wake-up sequences at runtime. The experimental results show that compared to a traditional fixed wake-up sequence approach, our strategy can reduce average wake-up time by as much as 45.04% with only 3.7% extra area overhead for the reconfiguration structure.

UR - http://www.scopus.com/inward/record.url?scp=85048837143&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85048837143&partnerID=8YFLogxK

U2 - 10.23919/DATE.2018.8342136

DO - 10.23919/DATE.2018.8342136

M3 - Conference contribution

AN - SCOPUS:85048837143

VL - 2018-January

SP - 901

EP - 904

BT - Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018

PB - Institute of Electrical and Electronics Engineers Inc.

ER -

Chiu KW, Chen YG, Lin I-C. An efficient NBTI-aware wake-up strategy for power-gated designs. In Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018. Vol. 2018-January. Institute of Electrical and Electronics Engineers Inc. 2018. p. 901-904 https://doi.org/10.23919/DATE.2018.8342136