An efficient pipeline architecture for deblocking filter in H.264/AVC

Chung Ming Chen, Chung-Ho Chen

Research output: Contribution to journalArticle

10 Citations (Scopus)

Abstract

In this paper, we study and analyze the computational complexity of deblocking filter in H.264/AVC baseline decoder based on SimpleScalar/ARM simulator. The simulation result shows that the memory reference, content activity check operations, and filter operations are known to be very time consuming in the decoder of this new video coding standard. In order to improve overall system performance, we propose a novel processing order with efficient VLSI architecture which simultaneously processes the horizontal filtering of vertical edge and vertical filtering of horizontal edge. As a result, the memory performance of the proposed architecture is improved by four times when compared to the software implementation. Moreover, the system performance of our design significantly outperforms the previous proposals.

Original languageEnglish
Pages (from-to)99-107
Number of pages9
JournalIEICE Transactions on Information and Systems
VolumeE90-D
Issue number1
DOIs
Publication statusPublished - 2007 Jan 1

Fingerprint

Pipelines
Data storage equipment
Image coding
Computational complexity
Simulators
Processing

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Computer Vision and Pattern Recognition
  • Electrical and Electronic Engineering
  • Artificial Intelligence

Cite this

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An efficient pipeline architecture for deblocking filter in H.264/AVC. / Chen, Chung Ming; Chen, Chung-Ho.

In: IEICE Transactions on Information and Systems, Vol. E90-D, No. 1, 01.01.2007, p. 99-107.

Research output: Contribution to journalArticle

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