Abstract
Multiple-input multiple-output (MIMO) techniques have been widely used in various wireless communication systems these days. QR factorization is a fundamental module yet computationally intensive used in many MIMO detection schemes. In this paper, a complex-valued QR factorization (CQRF) scheme realized via a sequence of real-value Givens rotations is first presented. An efficient CQRF design using coordinate rotation digital computer (CORDIC) modules is next developed. The design features a highly parallel architecture to support high throughput operations. One CQRF can be obtained in every 8 clock cycles. To reduce the circuit complexity, a pipelined CORDIC structure is also applied. The implementation results in TSMC 0.18-μm CMOS process indicate that the proposed design can achieve a throughput rate of 25MCQRFs per second while consuming only 103.7k gates in circuit complexity. Performance evaluation based on a composite index consisting of area and throughput rate also shows the advantages of the proposed design against other similar works.
Original language | English |
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Title of host publication | ISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems |
Pages | 1508-1511 |
Number of pages | 4 |
DOIs | |
Publication status | Published - 2012 |
Event | 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of Duration: 2012 May 20 → 2012 May 23 |
Other
Other | 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 |
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Country | Korea, Republic of |
City | Seoul |
Period | 12-05-20 → 12-05-23 |
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering