Abstract
Multiple-input multiple-output (MIMO) techniques have been widely used in various wireless communication systems these days. QR factorization is a fundamental module yet computationally intensive used in many MIMO detection schemes. In this paper, a complex-valued QR factorization (CQRF) scheme realized via a sequence of real-value Givens rotations is first presented. An efficient CQRF design using coordinate rotation digital computer (CORDIC) modules is next developed. The design features a highly parallel architecture to support high throughput operations. One CQRF can be obtained in every 8 clock cycles. To reduce the circuit complexity, a pipelined CORDIC structure is also applied. The implementation results in TSMC 0.18-μm CMOS process indicate that the proposed design can achieve a throughput rate of 25MCQRFs per second while consuming only 103.7k gates in circuit complexity. Performance evaluation based on a composite index consisting of area and throughput rate also shows the advantages of the proposed design against other similar works.
| Original language | English |
|---|---|
| Title of host publication | ISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems |
| Pages | 1508-1511 |
| Number of pages | 4 |
| DOIs | |
| Publication status | Published - 2012 |
| Event | 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of Duration: 2012 May 20 → 2012 May 23 |
Other
| Other | 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 |
|---|---|
| Country | Korea, Republic of |
| City | Seoul |
| Period | 12-05-20 → 12-05-23 |
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All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering
Cite this
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An efficient QR decomposition design for MIMO systems. / Lin, Jing Shiun; Hwang, Yin Tsung; Chu, Po Han; Shieh, Ming-Der; Fang, Shih Hao.
ISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems. 2012. p. 1508-1511 6271535.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - An efficient QR decomposition design for MIMO systems
AU - Lin, Jing Shiun
AU - Hwang, Yin Tsung
AU - Chu, Po Han
AU - Shieh, Ming-Der
AU - Fang, Shih Hao
PY - 2012
Y1 - 2012
N2 - Multiple-input multiple-output (MIMO) techniques have been widely used in various wireless communication systems these days. QR factorization is a fundamental module yet computationally intensive used in many MIMO detection schemes. In this paper, a complex-valued QR factorization (CQRF) scheme realized via a sequence of real-value Givens rotations is first presented. An efficient CQRF design using coordinate rotation digital computer (CORDIC) modules is next developed. The design features a highly parallel architecture to support high throughput operations. One CQRF can be obtained in every 8 clock cycles. To reduce the circuit complexity, a pipelined CORDIC structure is also applied. The implementation results in TSMC 0.18-μm CMOS process indicate that the proposed design can achieve a throughput rate of 25MCQRFs per second while consuming only 103.7k gates in circuit complexity. Performance evaluation based on a composite index consisting of area and throughput rate also shows the advantages of the proposed design against other similar works.
AB - Multiple-input multiple-output (MIMO) techniques have been widely used in various wireless communication systems these days. QR factorization is a fundamental module yet computationally intensive used in many MIMO detection schemes. In this paper, a complex-valued QR factorization (CQRF) scheme realized via a sequence of real-value Givens rotations is first presented. An efficient CQRF design using coordinate rotation digital computer (CORDIC) modules is next developed. The design features a highly parallel architecture to support high throughput operations. One CQRF can be obtained in every 8 clock cycles. To reduce the circuit complexity, a pipelined CORDIC structure is also applied. The implementation results in TSMC 0.18-μm CMOS process indicate that the proposed design can achieve a throughput rate of 25MCQRFs per second while consuming only 103.7k gates in circuit complexity. Performance evaluation based on a composite index consisting of area and throughput rate also shows the advantages of the proposed design against other similar works.
UR - http://www.scopus.com/inward/record.url?scp=84866606134&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84866606134&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2012.6271535
DO - 10.1109/ISCAS.2012.6271535
M3 - Conference contribution
SP - 1508
EP - 1511
BT - ISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems
ER -