An efficient VLSI architecture for convolutional code decoding

Yeu Horng Shiau, Pei-Yin Chen, Hung Yu Yang, Yi Ming Lin, Shi Gi Huang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

In this paper, an efficient VLSI architecture for convolutional code decoding algorithm is presented. This algorithm locates all erroneous segments of the received sequence and then applies our proposed decoder to these segments only. Besides, the clock-gating technique is used to disable the non-working registers of our design to further reduce the power consumption efficiently with no bit error rate (BER) degradation. Experimental calculations indicate that our design yields more power reduction than the conventional Viterbi decoder.

Original languageEnglish
Title of host publication2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program
Pages223-226
Number of pages4
DOIs
Publication statusPublished - 2010 Dec 1
Event2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Kaohsiung, Taiwan
Duration: 2010 Nov 182010 Nov 19

Publication series

Name2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program

Other

Other2010 International Symposium on Next-Generation Electronics, ISNE 2010
CountryTaiwan
CityKaohsiung
Period10-11-1810-11-19

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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