An efficient VLSI architecture for edge filtering in H.264/AVC

Chung Ming Chen, Chung Ho Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

In this paper, we study and analyze the computational complexity of H.264/AVC baseline profile decoder based on SimpleScalar/ARM simulator. The simulation result shows that the memory reference, the operations of content activity check, and the edge filtering are known to be very time consuming in the embedded system. In order to reduce the memory reference and improve overall system performance, we proposed a new efficient VLSI architecture to accelerate the processing of deblocking filter. The proposed architecture is called "Adaptive Edge Filtering Operation (AEFO)," which could be embedded in a platform-based architecture as a co-processor. As a result, the performance of the embedded system using AEFO is 1.66 times faster than software implementation. Moreover, the number of total memory references for loading and storage is reduced by 34% and 36% respectively.

Original languageEnglish
Title of host publicationProceedings of the Third IASTED International Conference on Circuits, Signals, and Systems, CSS 2005
EditorsV.G. Oklobdzija
Pages118-122
Number of pages5
Publication statusPublished - 2005 Dec 1
EventThird IASTED International Conference on Circuits, Signals, and Systems, CSS 2005 - Marina del Rey, CA, United States
Duration: 2005 Oct 242005 Oct 26

Publication series

NameProceedings of the Third IASTED International Conference on Circuits, Signals, and Systems, CSS 2005

Other

OtherThird IASTED International Conference on Circuits, Signals, and Systems, CSS 2005
CountryUnited States
CityMarina del Rey, CA
Period05-10-2405-10-26

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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