An efficient VLSI architecture for edge filtering in H.264/AVC

Chung Ming Chen; Chung Ho Chen

An efficient VLSI architecture for edge filtering in H.264/AVC

Chung Ming Chen, Chung Ho Chen

Institute of Computer and Communication Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

9 Citations (Scopus)

Abstract

In this paper, we study and analyze the computational complexity of H.264/AVC baseline profile decoder based on SimpleScalar/ARM simulator. The simulation result shows that the memory reference, the operations of content activity check, and the edge filtering are known to be very time consuming in the embedded system. In order to reduce the memory reference and improve overall system performance, we proposed a new efficient VLSI architecture to accelerate the processing of deblocking filter. The proposed architecture is called "Adaptive Edge Filtering Operation (AEFO)," which could be embedded in a platform-based architecture as a co-processor. As a result, the performance of the embedded system using AEFO is 1.66 times faster than software implementation. Moreover, the number of total memory references for loading and storage is reduced by 34% and 36% respectively.

Original language	English
Title of host publication	Proceedings of the Third IASTED International Conference on Circuits, Signals, and Systems, CSS 2005
Editors	V.G. Oklobdzija
Pages	118-122
Number of pages	5
Publication status	Published - 2005 Dec 1
Event	Third IASTED International Conference on Circuits, Signals, and Systems, CSS 2005 - Marina del Rey, CA, United States Duration: 2005 Oct 24 → 2005 Oct 26

Publication series

Name	Proceedings of the Third IASTED International Conference on Circuits, Signals, and Systems, CSS 2005

Other

Other	Third IASTED International Conference on Circuits, Signals, and Systems, CSS 2005
Country/Territory	United States
City	Marina del Rey, CA
Period	05-10-24 → 05-10-26

All Science Journal Classification (ASJC) codes

General Engineering

Cite this

@inproceedings{66e0f68fc0cb47c88028b69d42507733,

title = "An efficient VLSI architecture for edge filtering in H.264/AVC",

abstract = "In this paper, we study and analyze the computational complexity of H.264/AVC baseline profile decoder based on SimpleScalar/ARM simulator. The simulation result shows that the memory reference, the operations of content activity check, and the edge filtering are known to be very time consuming in the embedded system. In order to reduce the memory reference and improve overall system performance, we proposed a new efficient VLSI architecture to accelerate the processing of deblocking filter. The proposed architecture is called {"}Adaptive Edge Filtering Operation (AEFO),{"} which could be embedded in a platform-based architecture as a co-processor. As a result, the performance of the embedded system using AEFO is 1.66 times faster than software implementation. Moreover, the number of total memory references for loading and storage is reduced by 34\% and 36\% respectively.",

author = "Chen, \{Chung Ming\} and Chen, \{Chung Ho\}",

year = "2005",

month = dec,

day = "1",

language = "English",

isbn = "0889865094",

series = "Proceedings of the Third IASTED International Conference on Circuits, Signals, and Systems, CSS 2005",

pages = "118--122",

editor = "V.G. Oklobdzija",

booktitle = "Proceedings of the Third IASTED International Conference on Circuits, Signals, and Systems, CSS 2005",

note = "Third IASTED International Conference on Circuits, Signals, and Systems, CSS 2005 ; Conference date: 24-10-2005 Through 26-10-2005",

}

Chen, CM & Chen, CH 2005, An efficient VLSI architecture for edge filtering in H.264/AVC. in VG Oklobdzija (ed.), Proceedings of the Third IASTED International Conference on Circuits, Signals, and Systems, CSS 2005. Proceedings of the Third IASTED International Conference on Circuits, Signals, and Systems, CSS 2005, pp. 118-122, Third IASTED International Conference on Circuits, Signals, and Systems, CSS 2005, Marina del Rey, CA, United States, 05-10-24.

An efficient VLSI architecture for edge filtering in H.264/AVC. / Chen, Chung Ming; Chen, Chung Ho.
Proceedings of the Third IASTED International Conference on Circuits, Signals, and Systems, CSS 2005. ed. / V.G. Oklobdzija. 2005. p. 118-122 (Proceedings of the Third IASTED International Conference on Circuits, Signals, and Systems, CSS 2005).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - An efficient VLSI architecture for edge filtering in H.264/AVC

AU - Chen, Chung Ming

AU - Chen, Chung Ho

PY - 2005/12/1

Y1 - 2005/12/1

N2 - In this paper, we study and analyze the computational complexity of H.264/AVC baseline profile decoder based on SimpleScalar/ARM simulator. The simulation result shows that the memory reference, the operations of content activity check, and the edge filtering are known to be very time consuming in the embedded system. In order to reduce the memory reference and improve overall system performance, we proposed a new efficient VLSI architecture to accelerate the processing of deblocking filter. The proposed architecture is called "Adaptive Edge Filtering Operation (AEFO)," which could be embedded in a platform-based architecture as a co-processor. As a result, the performance of the embedded system using AEFO is 1.66 times faster than software implementation. Moreover, the number of total memory references for loading and storage is reduced by 34% and 36% respectively.

AB - In this paper, we study and analyze the computational complexity of H.264/AVC baseline profile decoder based on SimpleScalar/ARM simulator. The simulation result shows that the memory reference, the operations of content activity check, and the edge filtering are known to be very time consuming in the embedded system. In order to reduce the memory reference and improve overall system performance, we proposed a new efficient VLSI architecture to accelerate the processing of deblocking filter. The proposed architecture is called "Adaptive Edge Filtering Operation (AEFO)," which could be embedded in a platform-based architecture as a co-processor. As a result, the performance of the embedded system using AEFO is 1.66 times faster than software implementation. Moreover, the number of total memory references for loading and storage is reduced by 34% and 36% respectively.

UR - https://www.scopus.com/pages/publications/33244487199

UR - https://www.scopus.com/inward/citedby.url?scp=33244487199&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:33244487199

SN - 0889865094

T3 - Proceedings of the Third IASTED International Conference on Circuits, Signals, and Systems, CSS 2005

SP - 118

EP - 122

BT - Proceedings of the Third IASTED International Conference on Circuits, Signals, and Systems, CSS 2005

A2 - Oklobdzija, V.G.

T2 - Third IASTED International Conference on Circuits, Signals, and Systems, CSS 2005

Y2 - 24 October 2005 through 26 October 2005

ER -

An efficient VLSI architecture for edge filtering in H.264/AVC

Abstract

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All Science Journal Classification (ASJC) codes

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