An efficient VLSI architecture for edge filtering in H.264/AVC

Keyphrases

• H.264 Encoder 100%
• VLSI Architecture 100%
• Edge Filter 100%
• Memory References 75%
• Embedded Systems 50%
• Filtering Operation 50%
• Adaptive Edge 50%
• Decoder 25%
• Computational Complexity 25%
• Proposed Architecture 25%
• Software Implementation 25%
• Platform-Based 25%
• SimpleScalar 25%
• Overall System Performance 25%
• Deblocking Filter 25%
• Baseline Profile 25%
• Coprocessor 25%

Computer Science

• Memory Reference 100%
• Very large-scale integration (VLSI) architecture 100%
• Embedded System 66%
• Filtering Operation 66%
• Computational Complexity 33%
• Systems Performance 33%
• Software Implementation 33%
• deblocking filter 33%
• Baseline Profile 33%
• Coprocessor 33%