An efficient VLSI architecture for HMM-based speech recognition

Jer Min Jou; Yeu Horng Shiau; Chen Jen Huang

An efficient VLSI architecture for HMM-based speech recognition

Jer Min Jou, Yeu Horng Shiau, Chen Jen Huang

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

7 Citations (Scopus)

Abstract

A high speed and area-efficient VLSI architecture for HMM-based speech recognition is presented in this paper. It is designed by optimally applying the special property in speech recognition known as the left to right state transition model (LRM) and utilizing look-ahead pipelining techniques to break the recurrence of the speech recognition operations. In order to verify the proposed architecture, we have also designed and implemented it in a hardware prototyping with Xilinx FPGAs. The simulation and emulation results show the recognition speed can get 25,000 words per second under 92% recognition rate with 500 references and 10,000 test patterns by 10 speakers.

Original language	English
Title of host publication	ICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems
Pages	469-472
Number of pages	4
Publication status	Published - 2001 Dec 1
Event	8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001 - , Malta Duration: 2001 Sept 2 → 2001 Sept 5

Publication series

Name	Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Volume	1

Other

Other	8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001
Country/Territory	Malta
Period	01-09-02 → 01-09-05

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Cite this

@inproceedings{67487a91cd0a4d5e8c1b6c2e920efe3d,

title = "An efficient VLSI architecture for HMM-based speech recognition",

abstract = "A high speed and area-efficient VLSI architecture for HMM-based speech recognition is presented in this paper. It is designed by optimally applying the special property in speech recognition known as the left to right state transition model (LRM) and utilizing look-ahead pipelining techniques to break the recurrence of the speech recognition operations. In order to verify the proposed architecture, we have also designed and implemented it in a hardware prototyping with Xilinx FPGAs. The simulation and emulation results show the recognition speed can get 25,000 words per second under 92% recognition rate with 500 references and 10,000 test patterns by 10 speakers.",

author = "Jou, {Jer Min} and Shiau, {Yeu Horng} and Huang, {Chen Jen}",

year = "2001",

month = dec,

day = "1",

language = "English",

isbn = "0780370570",

series = "Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems",

pages = "469--472",

booktitle = "ICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems",

note = "8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001 ; Conference date: 02-09-2001 Through 05-09-2001",

}

Jou, JM, Shiau, YH & Huang, CJ 2001, An efficient VLSI architecture for HMM-based speech recognition. in ICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems., 957780, Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, vol. 1, pp. 469-472, 8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001, Malta, 01-09-02.

An efficient VLSI architecture for HMM-based speech recognition. / Jou, Jer Min; Shiau, Yeu Horng; Huang, Chen Jen.
ICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems. 2001. p. 469-472 957780 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; Vol. 1).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - An efficient VLSI architecture for HMM-based speech recognition

AU - Jou, Jer Min

AU - Shiau, Yeu Horng

AU - Huang, Chen Jen

PY - 2001/12/1

Y1 - 2001/12/1

N2 - A high speed and area-efficient VLSI architecture for HMM-based speech recognition is presented in this paper. It is designed by optimally applying the special property in speech recognition known as the left to right state transition model (LRM) and utilizing look-ahead pipelining techniques to break the recurrence of the speech recognition operations. In order to verify the proposed architecture, we have also designed and implemented it in a hardware prototyping with Xilinx FPGAs. The simulation and emulation results show the recognition speed can get 25,000 words per second under 92% recognition rate with 500 references and 10,000 test patterns by 10 speakers.

AB - A high speed and area-efficient VLSI architecture for HMM-based speech recognition is presented in this paper. It is designed by optimally applying the special property in speech recognition known as the left to right state transition model (LRM) and utilizing look-ahead pipelining techniques to break the recurrence of the speech recognition operations. In order to verify the proposed architecture, we have also designed and implemented it in a hardware prototyping with Xilinx FPGAs. The simulation and emulation results show the recognition speed can get 25,000 words per second under 92% recognition rate with 500 references and 10,000 test patterns by 10 speakers.

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M3 - Conference contribution

AN - SCOPUS:0038330951

SN - 0780370570

SN - 9780780370579

T3 - Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

SP - 469

EP - 472

BT - ICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems

T2 - 8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001

Y2 - 2 September 2001 through 5 September 2001

ER -

An efficient VLSI architecture for HMM-based speech recognition

Abstract

Publication series

Other

All Science Journal Classification (ASJC) codes

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