An efficient VLSI architecture of 1-D lifting discrete wavelet transform

Pei Yin Chen, Shung Chih Chen

Research output: Contribution to journalArticlepeer-review


An efficient VLSI architecture for 1-D lifting DWT is proposed in this paper. To achieve higherhardware utilization and higher throughput, the computations of all resolution levels are folded to both the same high-pass and low-pass filters. Besides, the number of registers in the folded architecture is minimized by using the generalized lifetime analysis. Owing to its regular and flexible structure, the design can be extended easily into different resolution levels, and its area is independent of the length of the 1-D input sequence. Compared with other known architectures, our design requires the least computing time for 1-D lifting DWT.

Original languageEnglish
Pages (from-to)2009-2014
Number of pages6
JournalIEICE Transactions on Electronics
Issue number11
Publication statusPublished - 2004 Nov

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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