An embedded processor based SOC test platform

Kuen-Jong Lee, Chia Yi Chu, Yu Ting Hong

Research output: Contribution to journalConference article

25 Citations (Scopus)

Abstract

In this paper we present a novel test platform for embedded processor based system-on-a-chip (SoC). The embedded processor is employed as a control kernel to execute the test programs for all the cores in the SoC. A dedicated Test Access Mechanism (TAM) controller is developed which controls the actual test procedure for each core such that no extra buffer is needed for individual cores. The TAM controller together with the test programs can execute scan-based testing, memory BIST and mixed-signal BIST. The platform can test cores wrapped by the standard boundary scan and the IEEE P1500 wrappers, as well as hierarchical and mixed-signal cores. Our methodology alleviates the need of expensive automatic test equipment (ATE), and hence can greatly reduce the total test cost. Experimental results show the effectiveness of the proposed test platform.

Original languageEnglish
Article number1465254
Pages (from-to)2983-2986
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
DOIs
Publication statusPublished - 2005 Dec 1
EventIEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan
Duration: 2005 May 232005 May 26

    Fingerprint

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this