In this paper we present a novel test platform for embedded processor based system-on-a-chip (SoC). The embedded processor is employed as a control kernel to execute the test programs for all the cores in the SoC. A dedicated Test Access Mechanism (TAM) controller is developed which controls the actual test procedure for each core such that no extra buffer is needed for individual cores. The TAM controller together with the test programs can execute scan-based testing, memory BIST and mixed-signal BIST. The platform can test cores wrapped by the standard boundary scan and the IEEE P1500 wrappers, as well as hierarchical and mixed-signal cores. Our methodology alleviates the need of expensive automatic test equipment (ATE), and hence can greatly reduce the total test cost. Experimental results show the effectiveness of the proposed test platform.
|Number of pages||4|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|Publication status||Published - 2005 Dec 1|
|Event||IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan|
Duration: 2005 May 23 → 2005 May 26
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering