An energy-delay efficient power management scheme for embedded system in multimedia applications

Wei Cheng Lin, Chung Ho Chen

Research output: Contribution to conferencePaperpeer-review

4 Citations (Scopus)

Abstract

High-performance embedded systems tend to use caches and memory hierarchy to speed up program execution. This increases DRAM idle time (inter-access time) and provides opportunity for reducing memory energy usage by performing memory state transition to a low-power mode. However, additional delay due to resynchronization may greatly increase the system response time. This work focuses on exploiting state transition techniques to reduce DRAM energy usage and also mitigating the penalty of resynchronization time. We propose a state transition technique based on address prediction that predicts the inter-access time between memory accesses. According to predicted inter-access time, the DRAM is directly put into a low-energy mode and transits back to the operation mode as the idle timer expires to avoid resynchronization overhead. Experiments using multimedia application show that the proposed scheme has achieved the best energy-delay performance than other previous policies.

Original languageEnglish
Pages869-872
Number of pages4
Publication statusPublished - 2004 Dec 1
Event2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan
Duration: 2004 Dec 62004 Dec 9

Other

Other2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
CountryTaiwan
CityTainan
Period04-12-0604-12-09

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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