TY - JOUR
T1 - An Energy-Efficient Conditional Biasing Write Assist with Built-In Time-Based Write-Margin-Tracking for Low-Voltage SRAM
AU - Huang, Chi Ray
AU - Chiou, Lih Yih
N1 - Funding Information:
Manuscript received January 18, 2021; revised March 26, 2021; accepted May 11, 2021. Date of publication June 8, 2021; date of current version August 2, 2021. This work was supported in part by the Ministry of Science and Technology, Taiwan, under Grant 109-2218-E-006-026 and Grant 110-2218-E-006-019; and in part by QualComm Tech., Inc., under Contract NAT-408931. (Corresponding author: Chi-Ray Huang.) The authors are with the Department of Electrical Engineering, National Cheng Kung University, Tainan 70101, Taiwan (e-mail: [email protected]; [email protected]).
Publisher Copyright:
© 1993-2012 IEEE.
PY - 2021/8
Y1 - 2021/8
N2 - Write assists (WAs), such as negative bitline and collapse supply voltage (VDD), can effectively improve the write{min} of static random access memory (SRAM) cells. The energy overhead associated with such assists is considerable due to the switching activities on high capacitive nodes for every write operation. In this brief, a conditional biasing WA with built-in time-based write-margin-tracking is proposed to avoid unnecessary assist for energy saving. The biasing voltage for assisting the write procedure is only adjusted during write failures and remains unchanged for native write-success cells. Compared with conventional WAs, the proposed design can reduce write energy by 29%-34% with a similar area overhead. In addition, silicon measurements have demonstrated that the proposed assist is functional for near-threshold operations and{DDmin} is reduced to 0.4 V.
AB - Write assists (WAs), such as negative bitline and collapse supply voltage (VDD), can effectively improve the write{min} of static random access memory (SRAM) cells. The energy overhead associated with such assists is considerable due to the switching activities on high capacitive nodes for every write operation. In this brief, a conditional biasing WA with built-in time-based write-margin-tracking is proposed to avoid unnecessary assist for energy saving. The biasing voltage for assisting the write procedure is only adjusted during write failures and remains unchanged for native write-success cells. Compared with conventional WAs, the proposed design can reduce write energy by 29%-34% with a similar area overhead. In addition, silicon measurements have demonstrated that the proposed assist is functional for near-threshold operations and{DDmin} is reduced to 0.4 V.
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U2 - 10.1109/TVLSI.2021.3084041
DO - 10.1109/TVLSI.2021.3084041
M3 - Article
AN - SCOPUS:85111062108
SN - 1063-8210
VL - 29
SP - 1586
EP - 1590
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 8
M1 - 9448190
ER -