In this paper, we propose a dual-edge triggered and dual-Vth level converting flip-flop (LCFF). The LCFF utilizes many energy-saving features that can be used in a multi-Vdd and multi-Vth system. A novel power-aware latch structure is designed to eliminate the internal power during transition. When operated in sleep mode, the power-aware latch will switch to low-leakage mode and still retain its data. Experimental results show that the proposed LCFF has the lowest PDP among compared FFs.
|Number of pages||4|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|Publication status||Published - 2007|
|Event||2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 - New Orleans, LA, United States|
Duration: 2007 May 27 → 2007 May 30
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering