An enhanced boundary scan architecture for inter-die interconnect leakage measurement in 2.5D and 3D packages

Pok Man Preston Law, Cheng Wen Wu, Long Yi Lin, Hao Chiao Hong

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

3D-IC is a solution to achieve lower cost and higher performance as the transistor density doubles every 18 months following Moore's law. In recent years, Integrated Fan-Out Wafer-Level Chip-Scale Packaging (InFO WLCSP) is one of the most promising packaging technologies for 3D-IC. In InFO WLCSP, there are some inter-die interconnects. We cannot access these interconnects directly. Therefore, it causes 1-2% test coverage loss. As a result, a built-in self-test (BIST) or other design-for-test (DFT) methodology is necessary to test these interconnects. It is easy to detect open defects and short defects leading to large leakage currents with conventional test methods. However, defects leading to small leakage currents are hard to detect, so we focus on these defects in this work. In this paper, we propose a scheme to measure the small leakage current of these inter-die interconnects. The scheme uses IEEE 1149.1 boundary scan interface. Because boundary scan is a well-adopted standard, the scheme can be integrated into any electronic product easily. Beside four mandatory terminals, we add a reference current input. Users can apply current to compare it with the leakage current. For the input EBSC, two OR gates, a MUX, and a current digitizer are added and it is compared with the conventional BSC. A test chip is implemented to verify our design, which uses the one-polynine-metal (1P9M) 90nm CMOS technology. Measurement results show that the proposed scheme is able to measure the leakage current of the interconnect. In addition, with the dynamic range of 128nA, the current digitizer has 6-bit resolution.

Original languageEnglish
Title of host publicationProceedings - 2017 IEEE 26th Asian Test Symposium, ATS 2017
Place of PublicationTaipei
PublisherIEEE Computer Society
Pages1-6
Number of pages6
ISBN (Electronic)9781538624364
DOIs
Publication statusPublished - 2018 Jan 24
Event26th IEEE Asian Test Symposium, ATS 2017 - Taipei, Taiwan
Duration: 2017 Nov 272017 Nov 30

Publication series

NameProceedings of the Asian Test Symposium
ISSN (Print)1081-7735

Other

Other26th IEEE Asian Test Symposium, ATS 2017
CountryTaiwan
CityTaipei
Period17-11-2717-11-30

Fingerprint

Leakage currents
Packaging
Defects
Fans
Built-in self test
Transistors
Metals
Costs

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Law, P. M. P., Wu, C. W., Lin, L. Y., & Hong, H. C. (2018). An enhanced boundary scan architecture for inter-die interconnect leakage measurement in 2.5D and 3D packages. In Proceedings - 2017 IEEE 26th Asian Test Symposium, ATS 2017 (pp. 1-6). (Proceedings of the Asian Test Symposium). Taipei: IEEE Computer Society. https://doi.org/10.1109/ATS.2017.14
Law, Pok Man Preston ; Wu, Cheng Wen ; Lin, Long Yi ; Hong, Hao Chiao. / An enhanced boundary scan architecture for inter-die interconnect leakage measurement in 2.5D and 3D packages. Proceedings - 2017 IEEE 26th Asian Test Symposium, ATS 2017. Taipei : IEEE Computer Society, 2018. pp. 1-6 (Proceedings of the Asian Test Symposium).
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abstract = "3D-IC is a solution to achieve lower cost and higher performance as the transistor density doubles every 18 months following Moore's law. In recent years, Integrated Fan-Out Wafer-Level Chip-Scale Packaging (InFO WLCSP) is one of the most promising packaging technologies for 3D-IC. In InFO WLCSP, there are some inter-die interconnects. We cannot access these interconnects directly. Therefore, it causes 1-2{\%} test coverage loss. As a result, a built-in self-test (BIST) or other design-for-test (DFT) methodology is necessary to test these interconnects. It is easy to detect open defects and short defects leading to large leakage currents with conventional test methods. However, defects leading to small leakage currents are hard to detect, so we focus on these defects in this work. In this paper, we propose a scheme to measure the small leakage current of these inter-die interconnects. The scheme uses IEEE 1149.1 boundary scan interface. Because boundary scan is a well-adopted standard, the scheme can be integrated into any electronic product easily. Beside four mandatory terminals, we add a reference current input. Users can apply current to compare it with the leakage current. For the input EBSC, two OR gates, a MUX, and a current digitizer are added and it is compared with the conventional BSC. A test chip is implemented to verify our design, which uses the one-polynine-metal (1P9M) 90nm CMOS technology. Measurement results show that the proposed scheme is able to measure the leakage current of the interconnect. In addition, with the dynamic range of 128nA, the current digitizer has 6-bit resolution.",
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Law, PMP, Wu, CW, Lin, LY & Hong, HC 2018, An enhanced boundary scan architecture for inter-die interconnect leakage measurement in 2.5D and 3D packages. in Proceedings - 2017 IEEE 26th Asian Test Symposium, ATS 2017. Proceedings of the Asian Test Symposium, IEEE Computer Society, Taipei, pp. 1-6, 26th IEEE Asian Test Symposium, ATS 2017, Taipei, Taiwan, 17-11-27. https://doi.org/10.1109/ATS.2017.14

An enhanced boundary scan architecture for inter-die interconnect leakage measurement in 2.5D and 3D packages. / Law, Pok Man Preston; Wu, Cheng Wen; Lin, Long Yi; Hong, Hao Chiao.

Proceedings - 2017 IEEE 26th Asian Test Symposium, ATS 2017. Taipei : IEEE Computer Society, 2018. p. 1-6 (Proceedings of the Asian Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Law PMP, Wu CW, Lin LY, Hong HC. An enhanced boundary scan architecture for inter-die interconnect leakage measurement in 2.5D and 3D packages. In Proceedings - 2017 IEEE 26th Asian Test Symposium, ATS 2017. Taipei: IEEE Computer Society. 2018. p. 1-6. (Proceedings of the Asian Test Symposium). https://doi.org/10.1109/ATS.2017.14