An enhanced DLX-based superscalar system simulator

Chung-Ho Chen, Akida Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We have designed a DLX-based superscalar processor simulator. This simulator provides many more functions than its predecessors developed elsewhere. We have added trap handlers and required C functions in the system so that most of the SPEC92 programs now run on the simulator. In addition, this simulator is fully configurable and re-configurable. Specifically, the following options and functions are provided by the simulator. • Central window versus distributed reservation stations. • Branch prediction mechanisms using static or dynamic schemes. The later provides branch target buffer and branch history table. • Configurable functional units. • A fully configurable KNL non-blocking cache structure incorporated in the simulator. (K: the number of ways. N: the number of cache lines in a way. L: line size). Split versus unified option and cm + βmL/D memory latency model. • Better debugging functions allowing the interruption of the simulation, reconfiguration, restart in a cycle-by-cycle fashion, or run to the end. • NT/Win95 platform ready. This DLX-based superscalar simulator is instruction-driven, which offers richer educational features than most of the trace-driven simulators. For information about this simulator, please refer to http://com.el.yuntech.edu.tw.

Original languageEnglish
Title of host publicationProceedings of the 1997 Workshop on Computer Architecture Education, WCAE-3 1997 at HPCA-3
PublisherAssociation for Computing Machinery, Inc
ISBN (Electronic)9781450347396
DOIs
Publication statusPublished - 1995 Jan 1
Event3rd Annual Workshop on Computer Architecture Education, WCAE 1997 - San Antonio, United States
Duration: 1997 Feb 11997 Feb 5

Publication series

NameProceedings of the 1997 Workshop on Computer Architecture Education, WCAE-3 1997 at HPCA-3

Other

Other3rd Annual Workshop on Computer Architecture Education, WCAE 1997
CountryUnited States
CitySan Antonio
Period97-02-0197-02-05

Fingerprint

Simulators
instruction
simulation
history
Data storage equipment

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Education

Cite this

Chen, C-H., & Wu, A. (1995). An enhanced DLX-based superscalar system simulator. In Proceedings of the 1997 Workshop on Computer Architecture Education, WCAE-3 1997 at HPCA-3 (Proceedings of the 1997 Workshop on Computer Architecture Education, WCAE-3 1997 at HPCA-3). Association for Computing Machinery, Inc. https://doi.org/10.1145/1275165.1275170
Chen, Chung-Ho ; Wu, Akida. / An enhanced DLX-based superscalar system simulator. Proceedings of the 1997 Workshop on Computer Architecture Education, WCAE-3 1997 at HPCA-3. Association for Computing Machinery, Inc, 1995. (Proceedings of the 1997 Workshop on Computer Architecture Education, WCAE-3 1997 at HPCA-3).
@inproceedings{cdec16aee07742a6afecc0ce0b341e14,
title = "An enhanced DLX-based superscalar system simulator",
abstract = "We have designed a DLX-based superscalar processor simulator. This simulator provides many more functions than its predecessors developed elsewhere. We have added trap handlers and required C functions in the system so that most of the SPEC92 programs now run on the simulator. In addition, this simulator is fully configurable and re-configurable. Specifically, the following options and functions are provided by the simulator. • Central window versus distributed reservation stations. • Branch prediction mechanisms using static or dynamic schemes. The later provides branch target buffer and branch history table. • Configurable functional units. • A fully configurable KNL non-blocking cache structure incorporated in the simulator. (K: the number of ways. N: the number of cache lines in a way. L: line size). Split versus unified option and cm + βmL/D memory latency model. • Better debugging functions allowing the interruption of the simulation, reconfiguration, restart in a cycle-by-cycle fashion, or run to the end. • NT/Win95 platform ready. This DLX-based superscalar simulator is instruction-driven, which offers richer educational features than most of the trace-driven simulators. For information about this simulator, please refer to http://com.el.yuntech.edu.tw.",
author = "Chung-Ho Chen and Akida Wu",
year = "1995",
month = "1",
day = "1",
doi = "10.1145/1275165.1275170",
language = "English",
series = "Proceedings of the 1997 Workshop on Computer Architecture Education, WCAE-3 1997 at HPCA-3",
publisher = "Association for Computing Machinery, Inc",
booktitle = "Proceedings of the 1997 Workshop on Computer Architecture Education, WCAE-3 1997 at HPCA-3",

}

Chen, C-H & Wu, A 1995, An enhanced DLX-based superscalar system simulator. in Proceedings of the 1997 Workshop on Computer Architecture Education, WCAE-3 1997 at HPCA-3. Proceedings of the 1997 Workshop on Computer Architecture Education, WCAE-3 1997 at HPCA-3, Association for Computing Machinery, Inc, 3rd Annual Workshop on Computer Architecture Education, WCAE 1997, San Antonio, United States, 97-02-01. https://doi.org/10.1145/1275165.1275170

An enhanced DLX-based superscalar system simulator. / Chen, Chung-Ho; Wu, Akida.

Proceedings of the 1997 Workshop on Computer Architecture Education, WCAE-3 1997 at HPCA-3. Association for Computing Machinery, Inc, 1995. (Proceedings of the 1997 Workshop on Computer Architecture Education, WCAE-3 1997 at HPCA-3).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - An enhanced DLX-based superscalar system simulator

AU - Chen, Chung-Ho

AU - Wu, Akida

PY - 1995/1/1

Y1 - 1995/1/1

N2 - We have designed a DLX-based superscalar processor simulator. This simulator provides many more functions than its predecessors developed elsewhere. We have added trap handlers and required C functions in the system so that most of the SPEC92 programs now run on the simulator. In addition, this simulator is fully configurable and re-configurable. Specifically, the following options and functions are provided by the simulator. • Central window versus distributed reservation stations. • Branch prediction mechanisms using static or dynamic schemes. The later provides branch target buffer and branch history table. • Configurable functional units. • A fully configurable KNL non-blocking cache structure incorporated in the simulator. (K: the number of ways. N: the number of cache lines in a way. L: line size). Split versus unified option and cm + βmL/D memory latency model. • Better debugging functions allowing the interruption of the simulation, reconfiguration, restart in a cycle-by-cycle fashion, or run to the end. • NT/Win95 platform ready. This DLX-based superscalar simulator is instruction-driven, which offers richer educational features than most of the trace-driven simulators. For information about this simulator, please refer to http://com.el.yuntech.edu.tw.

AB - We have designed a DLX-based superscalar processor simulator. This simulator provides many more functions than its predecessors developed elsewhere. We have added trap handlers and required C functions in the system so that most of the SPEC92 programs now run on the simulator. In addition, this simulator is fully configurable and re-configurable. Specifically, the following options and functions are provided by the simulator. • Central window versus distributed reservation stations. • Branch prediction mechanisms using static or dynamic schemes. The later provides branch target buffer and branch history table. • Configurable functional units. • A fully configurable KNL non-blocking cache structure incorporated in the simulator. (K: the number of ways. N: the number of cache lines in a way. L: line size). Split versus unified option and cm + βmL/D memory latency model. • Better debugging functions allowing the interruption of the simulation, reconfiguration, restart in a cycle-by-cycle fashion, or run to the end. • NT/Win95 platform ready. This DLX-based superscalar simulator is instruction-driven, which offers richer educational features than most of the trace-driven simulators. For information about this simulator, please refer to http://com.el.yuntech.edu.tw.

UR - http://www.scopus.com/inward/record.url?scp=84976539631&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84976539631&partnerID=8YFLogxK

U2 - 10.1145/1275165.1275170

DO - 10.1145/1275165.1275170

M3 - Conference contribution

T3 - Proceedings of the 1997 Workshop on Computer Architecture Education, WCAE-3 1997 at HPCA-3

BT - Proceedings of the 1997 Workshop on Computer Architecture Education, WCAE-3 1997 at HPCA-3

PB - Association for Computing Machinery, Inc

ER -

Chen C-H, Wu A. An enhanced DLX-based superscalar system simulator. In Proceedings of the 1997 Workshop on Computer Architecture Education, WCAE-3 1997 at HPCA-3. Association for Computing Machinery, Inc. 1995. (Proceedings of the 1997 Workshop on Computer Architecture Education, WCAE-3 1997 at HPCA-3). https://doi.org/10.1145/1275165.1275170