TY - GEN
T1 - An enhanced double-TSV Scheme for defect tolerance in 3D-IC
AU - Shih, Hsiu Chuan
AU - Wu, Cheng Wen
PY - 2013/10/21
Y1 - 2013/10/21
N2 - Die stacking based on Through-Silicon Via (TSV) is considered as an efficient way to reducing power consumption and form factor. In the current stage, the failure rate of TSV is still high, so some type of defect tolerance scheme is required. Meanwhile, the concept of double-via, which is normally used in traditional layer to layer interconnection, can be one of the feasible tolerance schemes. Double-via/TSV has a benefit compared to TSV repair: it can eliminate the fuse configuration procedure as well as the fuse layer. However, double-TSV has a problem of signal degradation and leakage caused by short defects. In this work, an enhanced scheme for double-TSV is proposed to solve the short-defect problem through signal path division and VDD isolation. Result shows that the enhanced double-TSV can tolerate both open and short defects, with reasonable area and timing overhead.
AB - Die stacking based on Through-Silicon Via (TSV) is considered as an efficient way to reducing power consumption and form factor. In the current stage, the failure rate of TSV is still high, so some type of defect tolerance scheme is required. Meanwhile, the concept of double-via, which is normally used in traditional layer to layer interconnection, can be one of the feasible tolerance schemes. Double-via/TSV has a benefit compared to TSV repair: it can eliminate the fuse configuration procedure as well as the fuse layer. However, double-TSV has a problem of signal degradation and leakage caused by short defects. In this work, an enhanced scheme for double-TSV is proposed to solve the short-defect problem through signal path division and VDD isolation. Result shows that the enhanced double-TSV can tolerate both open and short defects, with reasonable area and timing overhead.
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U2 - 10.7873/date.2013.302
DO - 10.7873/date.2013.302
M3 - Conference contribution
AN - SCOPUS:84885598125
SN - 9783981537000
T3 - Proceedings -Design, Automation and Test in Europe, DATE
SP - 1486
EP - 1489
BT - Proceedings - Design, Automation and Test in Europe, DATE 2013
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 16th Design, Automation and Test in Europe Conference and Exhibition, DATE 2013
Y2 - 18 March 2013 through 22 March 2013
ER -