An enhanced EDAC methodology for low power PSRAM

Po Yuan Chen, Yi Ting Yeh, Chao Hsun Chen, Jen Chieh Yeh, Cheng Wen Wu, Jeng Shen Lee, Yu Chang Lin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)


As feature size keeps shrinking, how to maintain the reliability becomes an important issue in IC production, especially for high density memory circuits. Error detection and correction (EDAC) schemes have been widely used for memory circuits for this purpose, but ordinary EDAC schemes are not suitable for memories with long codewords. The demand for low-power memory is increasing due to the growth in portable electronics markets. Power reduction in memories with DRAM-like cells can be done by reducing the refresh frequency, but the loss of data integrity should be taken care of seriously. To solve the above two issues, we propose a parallel encoding and decoding EDAC scheme, which can be used on memories with long codewords. Targeting refresh power reduction, we have implemented our scheme on an industrial pseudo SRAM (PSRAM), and have completed experiments. The major hardware penalty is the parity overhead that is 1/9, and the longest delay of our circuit is 3.6ns for the PSRAM fabricated by a 0.11/μm CMOS technology. With respect to the 70ns access time of the PSRAM, the proposed EDAC scheme can be integrated with the Read/Write operations without increasing the latency. Experimental results show that the refresh time can be extended greatly, without sacrificing reliability.

Original languageEnglish
Title of host publication2006 IEEE International Test Conference, ITC
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)1424402921, 9781424402922
Publication statusPublished - 2007 Dec 1
Event2006 IEEE International Test Conference, ITC - Santa Clara, CA, United States
Duration: 2006 Oct 222006 Oct 27

Publication series

NameProceedings - International Test Conference
ISSN (Print)1089-3539


Conference2006 IEEE International Test Conference, ITC
Country/TerritoryUnited States
CitySanta Clara, CA

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Applied Mathematics


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