An enhanced SRAM BISR design with reduced timing penalty

Li Ming Denq, Tzu Chiang Wang, Cheng Wen Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Abstract

Redundancy repair is an effective yield-enhancement technique for memories. There are many previously proposed repair methodologies, such as the popular repair methodology based on the concept of address remapping mechanism achieved by address comparison and address reconfiguration. However, a BISR design with a typical address remapping mechanism usually involves significant timing penalty. Therefore, we propose a new address remapping scheme with a write buffer to reduce the timing penalty. Our experiments show that with the proposed address remapping scheme and redundancy architecture, the timing penalty of our BISR scheme is the same with that of the Built-in Self-Test (BIST) circuit - only one multiplexer delay for both the inputs and outputs.

Original languageEnglish
Title of host publicationProceedings of the 15th Asian Test Symposium 2006
Pages25-30
Number of pages6
DOIs
Publication statusPublished - 2006 Dec 1
Event15th Asian Test Symposium 2006 - Fukuoka, Japan
Duration: 2006 Nov 202006 Nov 23

Publication series

NameProceedings of the Asian Test Symposium
Volume2006
ISSN (Print)1081-7735

Other

Other15th Asian Test Symposium 2006
CountryJapan
CityFukuoka
Period06-11-2006-11-23

All Science Journal Classification (ASJC) codes

  • Media Technology
  • Hardware and Architecture

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