An error tolerance scheme for 3D CMOS imagers

Hsiu Ming Chang, Jiun Lang Huang, Ding Ming Kwai, Kwang Ting Cheng, Cheng Wen Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)

Abstract

A three-dimensional (3D) CMOS imager constructed by stacking a pixel array of backside illuminated sensors, an analog-to-digital converter (ADC) array, and an image signal processor (ISP) array using micro-bumps (μbumps) and through-silicon vias (TSVs) is promising for high throughput applications. However, due to the direct mapping from pixels to ISPs, the overall yield relies heavily on the correctness of the μbumps, ADCs and TSVs - a single defect leads to the information loss of a tile of pixels. This paper presents an error tolerance scheme for the 3D CMOS imager that can still deliver high quality images in the presence of μbump, ADC, and/or TSV failures. The error tolerance is achieved by properly interleaving the connections from pixels to ADCs so that the corrupted data, if any, can be recovered in the ISPs. A key design parameter, the interleaving stride, is decided by analyzing the employed error correction algorithm. Architectural simulation results demonstrate that the error tolerance scheme enhances the effective yield of an exemplar 3D imager from 46% to 99%.

Original languageEnglish
Title of host publicationProceedings of the 47th Design Automation Conference, DAC '10
Pages917-922
Number of pages6
DOIs
Publication statusPublished - 2010 Sep 7
Event47th Design Automation Conference, DAC '10 - Anaheim, CA, United States
Duration: 2010 Jun 132010 Jun 18

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X

Other

Other47th Design Automation Conference, DAC '10
Country/TerritoryUnited States
CityAnaheim, CA
Period10-06-1310-06-18

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modelling and Simulation

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