An FET with a Source Tunneling Barrier Showing Suppressed Short-Channel Effects for Low-Power Applications

Yu Feng Hsieh, Si Hua Chen, Nan Yow Chen, Wen Jay Lee, Jyun Hwei Tsai, Chun Nan Chen, Meng-Hsueh Chiang, Darsen Lu, Kuo-Hsing Kao

Research output: Contribution to journalArticlepeer-review

2 Citations (Scopus)

Abstract

A device design technique using tunneling barriers (TBs) for reducing the short-channel effects (SCEs) is proposed. By introducing TBs at the source and drain junctions of a Si FET, the threshold voltage (Vth) roll-off can be significantly suppressed. This is because the TBs weaken the electrical coupling between drain bias and transmission/current spectrum in energy. Specifically, as compared with a conventional FET, the Vth roll-off for channel length reduction from 20 to 5 nm is mitigated by more than 40% when a thin TB is embedded at the source junction. This paper further reveals that the TB at the source junction dominates the physical mechanism minimizing the SCEs of the TBFET, and thus the device performance can be improved appreciably by removing the TB at the drain side and by decreasing the TB height at the source side.

Original languageEnglish
Pages (from-to)855-859
Number of pages5
JournalIEEE Transactions on Electron Devices
Volume65
Issue number3
DOIs
Publication statusPublished - 2018 Mar 1

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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