An HMAC processor with integrated SHA-1 and MD5 algorithms

Mao Yin Wang, Chih Pin Su, Chih Tsun Huang, Cheng Wen Wu

Research output: Contribution to conferencePaperpeer-review

38 Citations (Scopus)

Abstract

Cryptographic algorithms are prevalent and important in digital communications and storage, e.g., both SHA-1 and MD5 algorithms are widely used hash functions in IPSec and SSL for checking the data integrity. In this paper, we propose a hardware architecture for the standard HMAC function that supports both. Our HMAC design automatically generates the padding words and reuses the key for consecutive HMAC jobs that use the same key. We have also implemented the HMAC design in silicon. Compared with existing designs, our HMAC processor has lower hardware cost - 12.5% by sharing of the SHA-1 and MD5 circuitry and a little performance penalty.

Original languageEnglish
Pages456-458
Number of pages3
Publication statusPublished - 2004 Jun 1
EventProceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004 - Yokohama, Japan
Duration: 2004 Jan 272004 Jan 30

Conference

ConferenceProceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004
CountryJapan
CityYokohama
Period04-01-2704-01-30

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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