An investigation on anomalous hot-carrier-induced on-resistance reduction in n-type LDMOS transistors

In this paper, on-resistance $(R-{\rm on})$ degradation induced by hot-carrier injection in n-type lateral diffused metaloxidesemiconductor transistors with shallow trench isolation (STI) in the drift region is investigated. $R-{\rm on}$ unexpectedly decreases under medium- and high-gate voltage $(V-{ \rm gs})$ stress conditions. According to experimental data and technology computer-aided-design simulation results, the mechanisms responsible for anomalous $R-{\rm on}$ shift are proposed. When the device is stressed under medium $V-{\rm gs}$, hot-hole injection and trapping occur at the STI edge closest to the channel, resulting in $R-{\rm on}$ reduction. Interface trap generation $(\Delta N-{\rm it})$ occurs at the STI edge closest to the channel and nearby drift region, leading to $R-{\rm on}$ increase. For the device stressed under high $V-{\rm gs}$, $R-{\rm on}$ reduction is also attributed to hole trapping at the STI corner closest to the channel. $\Delta N-{\rm it}$ created by hot-electron injection at the STI edge closest to the drain dominates device characteristics and leads to $R-{\rm on}$ increase eventually. Based on the proposed $R-{\rm on}$ degradation mechanisms, an $R-{\rm on}$ degradation model is discussed and verified with experimental data.