An on chip ADC test structure

Yun Che Wen, Kuen Jong Lee

Research output: Contribution to journalConference articlepeer-review

38 Citations (Scopus)

Abstract

In this paper; a new built-in self-test structure to test the static specifications of analog to digital converters (ADCs) is presented. A ramp signal generated by an integrator serves as a test input signal. A specific range of this signal is divided into 2/sup n segments, with each segment corresponding to one output combination of an nbit counter; where n is the number of bits of the ADCs under test. The testing process is done with digital data processing by comparing the outputs of ADCs under test with the outputs of the n bit counter. Simple structure, low area overhead, and high speed are the advantages of the proposed test structure.

Original languageEnglish
Article number840042
Pages (from-to)221-225
Number of pages5
JournalProceedings -Design, Automation and Test in Europe, DATE
DOIs
Publication statusPublished - 2000 Dec 1
EventDesign, Automation and Test in Europe Conference and Exhibition 2000, DATE 2000 - Paris, France
Duration: 2000 Mar 272000 Mar 30

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Fingerprint Dive into the research topics of 'An on chip ADC test structure'. Together they form a unique fingerprint.

Cite this