An on-chip march pattern generator for testing embedded memory cores

W. L. Wang, K. J. Lee, J. F. Wang

Research output: Contribution to journalArticlepeer-review

16 Citations (Scopus)

Abstract

In this correspondence, we propose an effective approach to integrate 40 existing march algorithms into an embedded low hardware overhead test pattern generator to test the various kinds of word-oriented memory cores. Each march algorithm is characterized by several sets of up/down address orders, read/write signals, read/write data, and lengths of read/write operations. These characteristics are stored on chip so that any desired march algorithm can be generated with very little external control. An efficient procedure to reduce the memory storage for these characteristics is presented. We use only two programmable cyclic shift registers to generate the various read/write signals and data within the steps of the algorithms. Therefore, the proposed pattern generator is capable of generating any march algorithm with small area overhead.

Original languageEnglish
Pages (from-to)730-735
Number of pages6
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume9
Issue number5
DOIs
Publication statusPublished - 2001 Oct

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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