TY - JOUR
T1 - An On-Chip Multi-Voltage Power Converter With Leakage Current Prevention Using 0.18 μm High-Voltage CMOS Process
AU - Lo, Yi Kai
AU - Chen, Kuanfu
AU - Gad, Parag
AU - Liu, Wentai
N1 - Publisher Copyright:
© 2014 IEEE.
PY - 2016/2
Y1 - 2016/2
N2 - In this paper, we present an on-chip multi-voltage power converter incorporating of a quad-voltage timing-control rectifier and regulators to produce ±12 V and ±1.8 V simultaneously through inductive powering. The power converter achieves a PCE of 77.3% with the delivery of more than 100 mW to the implant. The proposed rectifier adopts a two-phase start-up scheme and mixed-voltage gate controller to avoid substrate leakage current. This current cannot be prevented by the conventional dynamic substrate biasing technique when using the high-voltage CMOS process with transistor threshold voltage higher than the turn-on voltage of parasitic diodes. High power conversion efficiency is achieved by 1) substrate leakage current prevention, 2) operating all rectifying transistors as switches with boosted gate control voltages, and 3) compensating the delayed turn-on and preventing reverse leakage current of rectifying switches with the proposed look-ahead comparator. This chip occupies an area of 970 μm × 4500 μm in a 0.18 μm 32 V HV CMOS process. The quad-voltage timing-control rectifier alone is able to output a high DC voltage at the range of [2.5 V, 25 V]. With this power converter, both bench-top experiment and in-vivo power link test using a rat model were validated.
AB - In this paper, we present an on-chip multi-voltage power converter incorporating of a quad-voltage timing-control rectifier and regulators to produce ±12 V and ±1.8 V simultaneously through inductive powering. The power converter achieves a PCE of 77.3% with the delivery of more than 100 mW to the implant. The proposed rectifier adopts a two-phase start-up scheme and mixed-voltage gate controller to avoid substrate leakage current. This current cannot be prevented by the conventional dynamic substrate biasing technique when using the high-voltage CMOS process with transistor threshold voltage higher than the turn-on voltage of parasitic diodes. High power conversion efficiency is achieved by 1) substrate leakage current prevention, 2) operating all rectifying transistors as switches with boosted gate control voltages, and 3) compensating the delayed turn-on and preventing reverse leakage current of rectifying switches with the proposed look-ahead comparator. This chip occupies an area of 970 μm × 4500 μm in a 0.18 μm 32 V HV CMOS process. The quad-voltage timing-control rectifier alone is able to output a high DC voltage at the range of [2.5 V, 25 V]. With this power converter, both bench-top experiment and in-vivo power link test using a rat model were validated.
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U2 - 10.1109/TBCAS.2014.2371695
DO - 10.1109/TBCAS.2014.2371695
M3 - Article
C2 - 25616076
AN - SCOPUS:84921463121
SN - 1932-4545
VL - 10
SP - 163
EP - 174
JO - IEEE transactions on biomedical circuits and systems
JF - IEEE transactions on biomedical circuits and systems
IS - 1
M1 - 7017455
ER -