An on-chip self-Test architecture with test patterns recorded in scan chains

Kuen Jong Lee, Pin Hao Tang, Michael A. Kochte

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)


This work proposes a novel test architecture that combines the advantages of both scan-based and built-in self-Test (BIST) designs. The main idea is to record (store) all required compressed test data in a novel scan chain structure such that the stored data can be extracted, reconstructed and decompressed into required deterministic patterns using an on-chip test controller with a test pattern decompressor. The recording of test data is achieved by modifying the connections between scan cells. Techniques to extract test data from the modified scan cells and to deliver decompressed test patterns to the modified scan cells are presented. The on-chip test controller can automatically generate all required control signals for the whole test procedure. This significantly reduces the requirements on external ATE. Experimental results on OpenSPARC T2, a publicly accessible 8-core processor containing 5.7M gates, show that all required test data for 100% testable stuck-At fault coverage can be stored in the scan chains of the processor with less than 3% total area overhead for the whole test architecture.

Original languageEnglish
Title of host publicationProceedings - 2016 IEEE International Test Conference, ITC 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781467387736
Publication statusPublished - 2016 Jul 2
Event47th IEEE International Test Conference, ITC 2016 - Fort Worth, United States
Duration: 2016 Nov 152016 Nov 17

Publication series

NameProceedings - International Test Conference
ISSN (Print)1089-3539


Other47th IEEE International Test Conference, ITC 2016
Country/TerritoryUnited States
CityFort Worth

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Applied Mathematics


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