An SOC test integration platform and its industrial realization

Kuo Liang Cheng, Jing Reng Huang, Chih Wea Wang, Chih Yen Lo, Li Ming Denq, Chih Tsun Huang, Cheng Wen Wu, Shin Wei Hung, Jye Yuan Lee

Research output: Contribution to journalConference articlepeer-review

7 Citations (Scopus)


One of the major costs in system-on-chip (SOC) development is test cost, especially the cost related to test integration. Although there have been plenty of research works on individual topics about SOC testing, few of them took into account the practical integration issues. In this paper, we stress the practical SOC test integration issues, including real problems found in test scheduling, test 10 reduction, timing of functional test, scan 10 sharing, etc. A test scheduling method is proposed based on our test architecture and test access mechanism (TAM), considering 10 resource constraints. Detailed scheduling further reduces the overall test time of the system chip. We also present a test wrapper architecture that supports the coexistence of scan test and functional test. The test integration platform has been applied to an industrial SOC case. The chip has been designed and fabricated. The measurement results justify the approach -simple and efficient, i.e., short test integration cost, short test time, and small area overhead.

Original languageEnglish
Pages (from-to)1213-1222
Number of pages10
JournalProceedings - International Test Conference
Publication statusPublished - 2004 Dec 1
EventProceedings - International Test Conference 2004 - Charlotte, NC, United States
Duration: 2004 Oct 262004 Oct 28

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Applied Mathematics


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