Abstract
One of the major costs in system-on-chip (SOC) development is test cost, especially the cost related to test integration. Although there have been plenty of research works on individual topics about SOC testing, few of them took into account the practical integration issues. In this paper, we stress the practical SOC test integration issues, including real problems found in test scheduling, test 10 reduction, timing of functional test, scan 10 sharing, etc. A test scheduling method is proposed based on our test architecture and test access mechanism (TAM), considering 10 resource constraints. Detailed scheduling further reduces the overall test time of the system chip. We also present a test wrapper architecture that supports the coexistence of scan test and functional test. The test integration platform has been applied to an industrial SOC case. The chip has been designed and fabricated. The measurement results justify the approach -simple and efficient, i.e., short test integration cost, short test time, and small area overhead.
| Original language | English |
|---|---|
| Pages (from-to) | 1213-1222 |
| Number of pages | 10 |
| Journal | Proceedings - International Test Conference |
| Publication status | Published - 2004 Dec 1 |
| Event | Proceedings - International Test Conference 2004 - Charlotte, NC, United States Duration: 2004 Oct 26 → 2004 Oct 28 |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
- Applied Mathematics
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An SOC test integration platform and its industrial realization. / Cheng, Kuo Liang; Huang, Jing Reng; Wang, Chih Wea; Lo, Chih Yen; Denq, Li Ming; Huang, Chih Tsun; Wu, Cheng Wen; Hung, Shin Wei; Lee, Jye Yuan.
In: Proceedings - International Test Conference, 01.12.2004, p. 1213-1222.Research output: Contribution to journal › Conference article
TY - JOUR
T1 - An SOC test integration platform and its industrial realization
AU - Cheng, Kuo Liang
AU - Huang, Jing Reng
AU - Wang, Chih Wea
AU - Lo, Chih Yen
AU - Denq, Li Ming
AU - Huang, Chih Tsun
AU - Wu, Cheng Wen
AU - Hung, Shin Wei
AU - Lee, Jye Yuan
PY - 2004/12/1
Y1 - 2004/12/1
N2 - One of the major costs in system-on-chip (SOC) development is test cost, especially the cost related to test integration. Although there have been plenty of research works on individual topics about SOC testing, few of them took into account the practical integration issues. In this paper, we stress the practical SOC test integration issues, including real problems found in test scheduling, test 10 reduction, timing of functional test, scan 10 sharing, etc. A test scheduling method is proposed based on our test architecture and test access mechanism (TAM), considering 10 resource constraints. Detailed scheduling further reduces the overall test time of the system chip. We also present a test wrapper architecture that supports the coexistence of scan test and functional test. The test integration platform has been applied to an industrial SOC case. The chip has been designed and fabricated. The measurement results justify the approach -simple and efficient, i.e., short test integration cost, short test time, and small area overhead.
AB - One of the major costs in system-on-chip (SOC) development is test cost, especially the cost related to test integration. Although there have been plenty of research works on individual topics about SOC testing, few of them took into account the practical integration issues. In this paper, we stress the practical SOC test integration issues, including real problems found in test scheduling, test 10 reduction, timing of functional test, scan 10 sharing, etc. A test scheduling method is proposed based on our test architecture and test access mechanism (TAM), considering 10 resource constraints. Detailed scheduling further reduces the overall test time of the system chip. We also present a test wrapper architecture that supports the coexistence of scan test and functional test. The test integration platform has been applied to an industrial SOC case. The chip has been designed and fabricated. The measurement results justify the approach -simple and efficient, i.e., short test integration cost, short test time, and small area overhead.
UR - http://www.scopus.com/inward/record.url?scp=18144379215&partnerID=8YFLogxK
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M3 - Conference article
AN - SCOPUS:18144379215
SP - 1213
EP - 1222
JO - IEEE International Test Conference (TC)
JF - IEEE International Test Conference (TC)
SN - 1089-3539
ER -