Analogue boundary scan architecture for DC and AC testing

Kuen-Jong Lee, Tian Pao Lee, Rong Chang Wen, Zhe Yi Lin

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

A new mixed-mode boundary scan architecture is developed. The digital part of this architecture complies with the IEEE Std 1149.1. For the analogue part, we propose a new boundary scan cell design and define 4 analogue test instructions. The control signals for each instruction are also described.

Original languageEnglish
Pages (from-to)704-705
Number of pages2
JournalElectronics Letters
Volume32
Issue number8
DOIs
Publication statusPublished - 1996 Apr 11

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All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Lee, Kuen-Jong ; Lee, Tian Pao ; Wen, Rong Chang ; Lin, Zhe Yi. / Analogue boundary scan architecture for DC and AC testing. In: Electronics Letters. 1996 ; Vol. 32, No. 8. pp. 704-705.
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Analogue boundary scan architecture for DC and AC testing. / Lee, Kuen-Jong; Lee, Tian Pao; Wen, Rong Chang; Lin, Zhe Yi.

In: Electronics Letters, Vol. 32, No. 8, 11.04.1996, p. 704-705.

Research output: Contribution to journalArticle

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