Analysis and control of hysteresis in PD/SOI CMOS

M. M. Pelella, J. G. Fossum, M. H. Chiang, G. O. Workman, C. R. Tretz

Research output: Contribution to journalConference articlepeer-review

13 Citations (Scopus)


A new methodology to characterize and analyze hysteresis in PD/SOI CMOS inverter-based circuits, including its true worst case, is defined, and new insight into the underlying physics is provided. The methodology is used to explore novel device/circuit designs for controlling hysteresis as the PD/SOI CMOS technology is scaled to <100nm.

Original languageEnglish
Pages (from-to)831-834
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
Publication statusPublished - 1999 Dec 1
Event1999 IEEE International Devices Meeting (IEDM) - Washington, DC, USA
Duration: 1999 Dec 51999 Dec 8

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry


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