Abstract
A new methodology to characterize and analyze hysteresis in PD/SOI CMOS inverter-based circuits, including its true worst case, is defined, and new insight into the underlying physics is provided. The methodology is used to explore novel device/circuit designs for controlling hysteresis as the PD/SOI CMOS technology is scaled to <100nm.
Original language | English |
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Pages (from-to) | 831-834 |
Number of pages | 4 |
Journal | Technical Digest - International Electron Devices Meeting |
Publication status | Published - 1999 |
Event | 1999 IEEE International Devices Meeting (IEDM) - Washington, DC, USA Duration: 1999 Dec 5 → 1999 Dec 8 |
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Electrical and Electronic Engineering
- Materials Chemistry