Analytic modeling for drain-induced barrier lowering phenomenon of the InGaP/InGaAs/GaAs pseudomorphic doped-channel field-effect transistor

A two-dimensional analytic model for characterizing the drain-induced barrier lowering (DIBL) phenomenon for the InGaP/InGaAs/GaAs pseudomorphic doped-channel field-effect transistor (PDCFET) is proposed. By solving nonlinear equations with the Newton method, this model provides a straightforward physical expression of the channel potential profile near or within the sub-threshold regime for short-channel effects. Calculations for a specified PDCFET device structure with a gate length of 0.25 μm have been conducted and results demonstrated that the pinch-off channel, at a gate-to-source bias of 1.2V, will resume current conduction as the potential barrier is lowered comparably to the thermal voltage when the drain bias elevates to 2.2V. This work presents a comprehensive investigation, and fast and convenient estimation for the short-channel effect, and can be extended to multichannel PDCFET structures.