Analyzing the BTI effect on multi-bit retention registers

Ing Chao Lin, Yao Te Wang, Shuen Shiang Yang, Yi Luen Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

As the Bias Temperature Instability (BTI) effect increase the threshold voltage of transistors and decrease transistors speed, it become a major problem for circuit reliability. Retention registers are used in the power gating architecture. These registers can keep the current states in the always-on blocks. However, they suffer from the BTI effect since the always-on block never is turned off. This paper proposes 2-bit and 3-bit parallel multi-bit retention registers and investigates the BTI effect on multi-bit retention registers. This paper also uses the selective transistor sizing technique to reduce the degradation. The proposed the multi-bit retention register architecture and design characteristics can reduce the significant area overhead. The experimental results show that compared with the original Dual Control Balloon Register (DCBR), the 2-bit and 3-bit retention registers can reduce area overhead by 27.1% and 34.7%, respectively.

Original languageEnglish
Title of host publicationIntelligent Systems and Applications - Proceedings of the International Computer Symposium, ICS 2014
EditorsWilliam Cheng-Chung Chu, Stephen Jenn-Hwa Yang, Han-Chieh Chao
PublisherIOS Press
Pages269-278
Number of pages10
ISBN (Electronic)9781614994831
DOIs
Publication statusPublished - 2015 Jan 1
EventInternational Computer Symposium, ICS 2014 - Taichung, Taiwan
Duration: 2014 Dec 122014 Dec 14

Publication series

NameFrontiers in Artificial Intelligence and Applications
Volume274
ISSN (Print)0922-6389

Other

OtherInternational Computer Symposium, ICS 2014
CountryTaiwan
CityTaichung
Period14-12-1214-12-14

All Science Journal Classification (ASJC) codes

  • Artificial Intelligence

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