Application-independent testing of 3-D field programmable gate array interconnect faults

Yen Lin Peng, Ding Ming Kwai, Yung Fa Chou, Cheng Wen Wu

Research output: Contribution to journalArticlepeer-review

5 Citations (Scopus)


3-D integration has been touted as an approach to reducing the lengths of critical paths in field-programmable gate arrays (FPGAs). A 3-D chip stacks a number of 2-D FPGA bare dies, interconnected by through-silicon vias (TSVs) and micro bumps, to attain a high packing density. However, the technology also introduces new types of defects, such as TSV void and microbump misalignment. Testing the interconnection faults becomes inevitable. In this paper, we present an automatic test pattern generator for open, short, and delay faults on 3-D FPGA interconnects by exploiting the regularity of switch matrix topology and forming repetitive paths with finite steps and with loop-back. The experimental results show that 12 test patterns (TPs) suffice to achieve 100% open fault coverage (FC). To detect all possible neighboring short faults, we need more than 40 TPs, whose number increases only slightly with the height of the 3-D FPGA. The TPs have high delay FC (96%) for 3-D FPGAs with the number of configurable logic blocks ranging from 50×, 50×2 to 50×,50×6, demonstrating the scalability of our method.

Original languageEnglish
Article number6459051
Pages (from-to)207-219
Number of pages13
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number2
Publication statusPublished - 2014 Feb 1

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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