This paper collates design concepts of lowpower gate driver circuits, and our related work is reviewed. Many approaches to power consumption amelioration have been developed and-focus on different parts of circuit structures. Recently, low-frequency clock signals are adopted to further reduce both power consumption and thin-film transistor (TFT) threshold voltage shifts (ΔVTH).
|Number of pages||4|
|Journal||Digest of Technical Papers - SID International Symposium|
|Publication status||Published - 2017|
|Event||SID Symposium, Seminar, and Exhibition 2017, Display Week 2017 - Los Angeles, United States|
Duration: 2017 May 21 → 2017 May 26
All Science Journal Classification (ASJC) codes