Application of low-frequency clock signals to gate driver circuits

Chin Lung Lin, Mao Hsun Cheng

Research output: Contribution to journalConference articlepeer-review

4 Citations (Scopus)

Abstract

This paper collates design concepts of lowpower gate driver circuits, and our related work is reviewed. Many approaches to power consumption amelioration have been developed and-focus on different parts of circuit structures. Recently, low-frequency clock signals are adopted to further reduce both power consumption and thin-film transistor (TFT) threshold voltage shifts (ΔVTH).

Original languageEnglish
Pages (from-to)64-67
Number of pages4
JournalDigest of Technical Papers - SID International Symposium
Volume48
Issue number1
DOIs
Publication statusPublished - 2017 Jan 1
EventSID Symposium, Seminar, and Exhibition 2017, Display Week 2017 - Los Angeles, United States
Duration: 2017 May 212017 May 26

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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